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TPS536C7: SYNC function

user4811888
Intellectual 530 points
Part Number: TPS536C7

Hi expert,

This device has SYNC pin and has options for SYNC mode: CLF Mode(Int CLK) and PLL Mode(ext CLK). It can be configured through E4h.

My questions:

1. Why do these discerptions below from two places(DS, TRM) look different? In DS, it looks that only one of these two modes can be realized. 

But in TRM, these two enable signals are independent. Can CLF loop and PLL loop operate at the same time? Also, the E4h[14] looks no relationship with mode enabled.

2. It looks too me that CLF loop is a slow closed-loop frequency-loop to adjust on-time, to ensure fsw close to the target fsw we set, especially when load current is high.

However, frequency control is claimed one per channel, e.g. channel A is configured with 12 ph in total. Does it mean phase 1- phase 12 will share the same frequency control output of Δton, along with PWM order 0 only?

3. PLL loop is for phase tracking with specific CLK only, that means we can use two TPS536C7 to realize 24ph interleaving, right?

  • +1
    TI__Genius 11095 points

    Hello,

    1- The hardware is configurable such that other modes are possible, but not all of these modes make sense. So when we wrote the datasheet, we pulled out only the most common ones for the electrical spec table. Technically, yes, the configuration will not prevent you from using (PLL mode + Internal Sync) or (CLF mode + external Sync) but these are really uncommon, and not really necessary. I actually have not seen an application for those other modes.

    2-  The CLF/PLL loop does indeed slowly adjust the on-time of Phase 1 (actually whatever phase you assign to PHASE ORDER 0 through PHASE CONFIG) only. The same Delta-Ton is applied to all of the phases to match the frequency, and then the current sharing loop independently balances the current in each phase. 

    3- Yes, the purpose of the PLL is to enable phase spreading of multiple converters on the same board (or channel A vs. Channel B on the same TPS536C7). This controller does not current share between two loops. It is more for spreading mutiple converters. 

  • 0 in reply to Matt Schurmann
    Intellectual 530 points

    Hello,

    Thanks for your clear explanation!

    For no.1, when external CLK is used, can I enable PLL and CLF loop at the same time? Will they conflict with each other?

    From my expectation, I might hope both exact PWM order-0 phase degree, and PWM order-0 frequency, will be controlled in closed-loop. 

  • 0 in reply to user4811888
    TI__Genius 11095 points

    I do not recommend using the PLL and CLF loops at the same time. 

    Yes, PWM-order-0 will be synchronized to Clock, with a few hundred ns delay, and offset by whatever phase shift you program.