Hi team,
I would like to know the PG and PG delay pin can be left open when it is not used.
I found below thread, but I just would like to double check since PG behavior is used internal to the device as below and Figure 15 state diagram.
Is the following PG signal device internal signal?
"Therefore, the logic-input signals (IGN_PWRL and PS) are considered to be valid only when the PG pin reaches the high level.
When the output voltage is less than the PG undervoltage threshold (essentially the output voltage is falling) for a
time longer than the PG deglitch filter time, the PG pin is pulled low. When the PG pin is low, the level of the PS
and IGN_PWRL pins is interpreted as low, regardless of the actual level."
regards,
