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CSD17312Q5: Mosfet and thermal management

Part Number: CSD17312Q5
Other Parts Discussed in Thread: CSD17577Q5A

Hi Guys, 

Please help me to clarify to our customer about the mosfet and thermal management of CSD17312Q5.

I have posted the full inquiry of our customer below for more details:

I'm working to use a Texas Instruments mosfet (model CSD17312Q5) as a low side switch to turn a Peltier cell on and off. The electrical power consumption of the cell is high (10 Amps at 24V), but this mosfet should be able to handle it, according to the datasheet. I will definitely have to pay attention to the heating problem. This is the first time that I use a mosfet with such a large electric current (I am a beginner, I have used mosfets only for educational purposes, to turn some leds on and off), and there are some questions I would like to ask about the thermal management of the mosfet. Before choosing this model of T.E. mosfet, I looked at the datasheets of many other similar mosfets; almost all of them had in common some indications regarding the correct dissipation of heat. In particular, in order to better dissipate the heat, they suggested mounting the mosfet “on a 1-inch² (6.45-cm²), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB ”.

In detail, it was always the pins connected to the Drain that were connected to this large copper pad, not the pins connected to the Source.
Only in a few cases have I seen some special mosfets in which above the body of the mosfet there was a small metal part connected to the Source, and a small aluminum radiator could be mounted above it, so as to also cool the Source ( as well as the Drain).
I would like to ask two questions:

1) The “1-inch², 2-oz. Cu pad ”must be exposed (as if it were a normal soldering pad) or can it be covered by the soldermask? I ask because I believe soldermask limits thermal disposal, although not as much as electrical conductivity.

2) Unfortunately, I cannot use a FR4 PCB with 2 oz of copper: I am forced to use a FR4 PCB with only 1 oz of copper. However, it is a double-layered FR4, so I can use both faces to disperse the heat, also thanks to the fact that the bottom face will still be in the air. In all the mosfets I have seen (except the special ones I mentioned a little above) it is always the pins of the Drain that take care of the heat dissipation; using both faces of a double sided FR4 PCB is it better that both faces are connected to the Drain pin, or can I connect the top face pad to the Drain pin and the bottom face pad to the Source pin? Is it useful to connect the Source pins to a copper pad to cool it down, or is it useless?

Thank you in advance for your support. 

Best regards,


  • Hi Jonathan,

    Thanks for promoting TI FETs at your customer. Below you will find some useful links to technical information available on the MOSFET Support & training page regarding thermal impedance and power dissipation capabilities of various TI FET packages. There is also a load switch FET selection tool that calculates the power dissipation in the FET allowing the customer to compare up to 3 different devices for their application.

    The 1-inch², 2 oz. copper pad is a standard used by TI and many other FET vendors for measuring and specifying thermal impedance. It is not a requirement and most customers don't use that large of a pad due to space constraints. The primary path to remove heat from the 5x6mm SON package is thru the large thermal pad on the bottom of the device which the drain of the FET sits on, and into the PCB. The source of the FET is connected to the pins either using wire bonds (Q5A package) or a copper clip (Q5 & Q5B). The copper clip minimizes parasitic inductance and resistance and provides a better path for heat dissipation thru the source pins into the PCB. Maximizing the copper area on both the drain and source pins is recommended to remove heat from the device. Furthermore, thermal vias can be used to provide a path to spread the heat to inner layers and to the backside of the PCB.

    I've seen the copper both exposed and covered with solder mask in various PCB layouts. I don't believe there is a big difference in PCB-to-ambient thermal impedance using either approach. Usually, this is dictated by the customer's design rules. The CSD17312Q5 is a low on resistance (1.4mOhm typical at VGS =4.5V) and can easily conduct 10A of current. The estimated conduction loss at ID = 10A, VGS = 5V & TJ = 75C is only 335mW. With a good layout on a multilayer PCB, this package can dissipate a maximum of 3W. There are a number of lower cost options in the same size package which will increase the conduction loss but still within acceptable limits. For example, the CSD17577Q5A will dissipate about 720mW at a much lower cost in a 5x6mm SON package. This FET is also available in a smaller, 3.3x3.3mm SON package.

    Best Regards,

    John Wallace

    TI FET Applications