TL494: Dead-Time

Hi Ishiwata,

Thanks for connecting through E2E. Answer to your questions are as below:

(1)
Please tell me the variation of 0.1V of Dead-Time Control Comparator in the block diagram below.
Also, what is the 0.7V variation of the PWM Comparator?

• The offset voltages shown in the block diagram you highlighted are not measured test parameters and not possible to specify the total variation. They are not trimmed for accuracy like a bandgap reference. A safe estimate might be +/-10%.

(2)
9.3.3 Please tell me about the description of Dead-time Control.
"An internal offset of 110 mV ensures a minimum dead time of ~ 3% with the dead-time control input grounded."
Although it is described like this, it was reported that it was about 10% when measured by the customer.
Why is the Dead-time 10%?

• When the DTC input is connected to GND, the internal ~100 mV offset ensures a minimum dead time of ~3%. The value could be greater than 3% according to some variation on the offset voltage you asked about in the previous question. It also matters how the DTC pin is connected to GND. If DTC tied directly to a quiet digital GND through the PCB, this is the best you can expect and will give the closest result to ~3% DT. If the GND is noisy, the average voltage seen by DTC can be mV's above GND. If the DTC pin is actively pulled to GND through an external NMOS, NPN or comparator, there will remain some offset voltage seen at DTC during the active state and this will also result in a minimum DT greater than ~3% stated in the data sheet.

Regards,

Steve M

Ishiwata,

0.57 V seems high and the DTC pin voltage looks like absolute GND. Try increasing CT and decreasing RT (maintain the same frequency) to slow down the downslope of the RAMP signal. Measure and compare to the waveform you provided. Are these waveforms taken from a real circuit or simulation file?

Regards,

Steve M