LP5562: i2c data hold time measurement

Allan Fan

Part Number: LP5562

Hi Expert,

The LP5562 i2c timing spec for data hold time minimum is 50ns but customer only got 40ns. In DS figure2, it seems the measure start point is from 0V?

From i2c spec, the data hold time is measured from 30% of fall time. By measuring from that, it can pass 50ns requirement.

note: i2c communication is no problem

Could you please clarify what’s the correct data hold time measure start point defined in our DS?

The second question, the i2c spec data hold time minimum is 5ns, but why LP5562 need 50ns? Is it a must meet requirement?

Thanks.

Allan

over 4 years ago

0 Frank Qiu over 4 years ago

TI__Genius 15776 points

HI Monet, could you help in this case.

0 Monet Xu over 4 years ago

TI__Genius 9255 points

Hi Allan,

There may be some different in different DS for I2C timing parameters' test. Please refer to the Figure 2 in DS of LP5562. The measure start point should to be 0 volt.

For question 2, the I2C communication speed in figure 4 which provided by you is low than the speed of LP5562, so there would be some difference.

Best Regard

Monet Xu

0 Louisa Lin over 4 years ago in reply to Monet Xu

Prodigy 60 points

Hi Monet

According to the I2C standard, whether it is Standard mode (Freq: 0~100KHz) or Fast Mode (Freq: 0~400KHz), the minimum value of data hold time is defined as 0us.
We cannot understand why LP5562 requires a minimum of 50ns.
Can we follow the spec of the I2C standard?

Louisa

0 Frank Qiu over 4 years ago in reply to Louisa Lin

TI__Genius 15776 points

Hi Monet, please help Louisa in this case.

0 Louisa Lin over 4 years ago in reply to Frank Qiu

Prodigy 60 points

Hi Monet

If we measure the falling 30% of CLK and 30% of Data rising, the time is about 76ns, such a measurement method and the result are OK?

Louisa

0 Monet Xu over 4 years ago in reply to Louisa Lin

TI__Genius 9255 points

Hi Louisa,

From the table attached in datasheet 6.6 Logic Interface Characteristics, The maximum of input low level is 0.2*VEN and minimum of input high level is 0.8 VEN. According to the spec, It will better to measure from the 20% of the falling time to 20% of the rising time. 30% of CLK and SDA is the common test parameter if the low level and high level of logic voltage spec don't be provided clearly, and the test error for both is not significant.

Best Regard

Monet Xu