LM25145: slow edges down to 100ns

Clint Miller

Prodigy 10 points

Part Number: LM25145

Can I slow the LM25145 edges down to 100ns by using a resistor in the gate?

Will slowing the edges down to 100ns create shoot-thru?

Will the adaptive dead-time work with the 100ns slow edge?

Will the adaptive dead-time run into an upper limit around 14ns?

over 4 years ago

0 Timothy Hegarty over 4 years ago

TI__Guru 73072 points

Hi Clint,

Are you adding a gate resistor on the high-side FET? Slowing down the SW voltage rise/fall times to 100ns will really hurt efficiency - is this for EMI mitigation?

Regards,

Tim

0 Clint Miller over 4 years ago in reply to Timothy Hegarty

Prodigy 10 points

Hi Tim,

1. Yes we would be adding a gate resistor. There is also a resistor in the boost supply.

2. Efficiency is a concern but we will be more concerned with the thermal problem of cooling the FET.

3. It is to reduce Ultrasound image artifacts at 10MHz that have been localized to specific dc-dc converters. I estimate the edge needs to be between 40ns and 100ns to reduce the harmonics at the 10MHz frequency.

Thanks,

Clint

0 Timothy Hegarty over 4 years ago in reply to Clint Miller

TI__Guru 73072 points

Thanks, Clint.

It will be very difficult to slow the falling edge to 100ns at full load. Would input filtering suffice to mitigate the problem? Also, you can use a shielded inductor to minimize radiated emissions.

For PCB power stage layout, take a look at this app note: https://www.ti.com/lit/an/snva803/snva803.pdf

Tim

0 Clint Miller over 4 years ago in reply to Timothy Hegarty

Prodigy 10 points

Hi Tim,

What is the slowest edge that the part will support?

The converter is too close to a sensitive receiver. Input filtering probably won't help (it is filtered though). If I change the layout I'll move it away from the receiver.

Thanks,

Clint

+1 Timothy Hegarty over 4 years ago in reply to Clint Miller

TI__Guru 73072 points

You can slow it down as much as needed (the gate driver is adaptive and measures when the SW voltage goes low to turn on the low-side FET). However, the efficiency will reduce significantly, meaning high power loss and FET temperature rise. Probably not a big deal if the output current is low.

Tim

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LM25145: slow edges down to 100ns