bq33100 EVSW available?

Garry, thank you!

We're very excited about this chip as our other solutions weren't nearly as elegant and we hope to use it in several products. Of course, our application involves one more cap than the bq33100 handles, six in series (ranging from 100F to 2000F). But, worst case, we'll use two chips configured for a 3S string of caps and consolidate the data we get from each with a microprocessor.

Out only concern is that we'll be dealing with very high current surge current levels from the caps, 200A - 1000A, up to 3 seconds long, and recharge current levels of approximately 150A-300A. We'll also be using the FAULT output to control a set of discharge FETs for short-circuit protection.

We can go as high as 1mOhm for the sense resistor (with high enough power ratings and lots of PCB copper) but will need to closely review the available firmware settings and calibration steps.

If we can do all of the above, we'll quickly lay out a board for the chip to handle much higher current levels either pulling the EVM chips or, hopefully, using samples.

Thanks again!

Hi John,

Its certainly an interesting approach to consider two bq33100's stacked on top of each other, but it will likely present some interesting voltage translation (or isolation) issues. Also, it will be virtually impossible to get all six caps to balance together. You might want to consider using just one bq33100 in "stack" mode. In that case, the balancing could be done with bleeding resistors across each cap, or a combination of resistors and opamps.

For very high current applications such as this, it may become impractical to measure the charge/discharge current unless the learning load can also be similar in magnitude - which is usually out of the question! For example, our ability to measure current is quite accurate, but if you try to use a 1 milliohm sense resistor and a 3A learning load, the bq33100 would have to accurately measure the 3 millivolts across the sense resistor when evaluating capacitance and ESR. I'm afraid offsets would be too much of a factor and resolution quite limited. A better solution may be to forego the monitoring of charge and discharge current, if you can, and focus on the learning load current only. We can provide a reference design for a 5S application that you might adapt for your application.

Rgds,

Doug Williams

Hi Doug,

I'd be very interested in seeing the 5S ref. design, thanks!

Yea, the 5S/6S design we're considering brings up all sorts of challenges that, we hope, are surmountable. This chip allows for some real benefits over what we thought would be a brute force, discrete, cap. management system and we hoped that with some creative thinking it would offer a much more elegant solution. Even though we'd be using it a tad differently than originally envisioned by its designers. :-))

One of the biggest challenges is that we need a 6S design to keep the caps below their max. voltage rating. We're working with our preferred cap vendor to determine what the life of the caps will be (obviously reduced) if we went to 5S at the same voltage level. I hate the idea of this but if we can get even a 2 year life, that's OK. The vendor, obviously, was horrified at first. But, we're hoping they'll give us the data we need to make a decision.

We knew we'd be adding digital isolation to a 2x3S design (using two bq33100 in series) but thought, hoping actually, that since all of the caps would be set to balance to the same voltage level that the differences between the two 3S strings would be minimal and only subject to part, production and calibration tolerances. All of the caps would be kept safe though and the balancing would be close enough to allow operation without any real impact on the overall performance of the 6S string. We would have to be very creative with controlling the FETs, but we felt that wasn't a big problem.

Hadn't considered using a single bq33100 in stack-mode though....very interesting. We're limited to using active-balancing because of severe quiescent current limitations, but that's not a problem (the circuits are easy and inexpensive). We do want to retain as much of the data gathering capabilities of the bq33100 though as it's the biggest reason we're considering it for this design (and three others). I'll have to review the datasheet regarding that as SOC, SOH, ESR increases and end-of-life indications are very important.

We can go to 20A for the learning load (perhaps higher) without problems but I understand your concern regarding the measurement of the current surges involved.  For these applications, we don't really need to measure these surges (would be nice though) but only need to determine SOC, SOH, Cap., etc. But, without accurate measurement of these high-amp pulses, I'm guessing that accurate Capacitance (and other) measurement just isn't possible?

Thank you for your time!

John,

The circuit for the 5S/100A supercap manager is attached. We also have an accompanying circuit available for a buck-boost (actually SEPIC) charger and high current ideal "oring" circuit if you are interested.

In this case, we had to use two charge FETs to get the job done without a big heatsink. Q100 turns on when the cap stack voltage is under 5V, then Q12 takes over at higher voltages. VSC is the output of the charger. Notice that only the learning load current passes through the sense resistor R55.

Rgds,

Doug

Thanks for the holdup schematic! I'd be very interested in seeing the diode or'ing schematic too. In fact, seeing any schematics using the bq33100/33101 helps with my understanding of the chip and the ways it can be used. If not too much trouble, please also post the schematic for the circuit that's for the SEPIC charger.

I'll be taking a much closer look at the 5S/100A circuit but I immediately noticed it uses a bq33101. Any info available on the differences between it and the bq33100?

Thank you!