TPS61086: Snuber Circuit

Hi Yamaguchi,

Please refer to the application note attached below to design the snubber, the value corresponds to several factors such as parasite parameters.

https://www.ti.com/lit/an/slva255/slva255.pdf?ts=1623035713638&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS61086

Best Regards,

Eric Yue

Hi Eric-san,

Thank you for providing the app note. It seems that the CPAR-Q1, LPAR1, and LPAR2 are the values which inside the IC. If you have the information, could you let me know? Does the CsigmaPAR# mean CPAR-Q1 + CPAR-D1?

Regards,

Yamaguchi

Hi Yamaguchi,

Yes, I think your understanding is correct.

Best Regards,

Eric Yue

Hi Eric-san,

Could you tell me the values of CPAR-Q1, LPAR1, and LPAR2?

Regards,

Yamaguchi

Hi Yamaguchi,

Sorry, I don't have specific values of these parameters. I think total value of parasitic inductance and capacitance including IC integrated and layout parameter can be obtained through ringing test without RC snubber, because it's relatively difficult to calculate or simulate parasite parameters. Maybe reserving the position in advance and optimizing RC snubber for board testing based on system requirements is a good choice.

Best Regards,

Eric Yue