Help with TPS40060 Design - Needed to make changes from Datasheet Design Equations - Power management forum - Power management

1. R ILIM , fixed to 91 K as the expected current protection is about 15 A.

While calculating using the formula in the data sheet ends up in 39 K (15A ×0.026)/11.5u +50mv/11.5u = 39K .

First, Rdson(max) needs to include thermal rise on Rdson. I would normally account for approximately 40% rise over temperature (allowing for 125C MOSFET die temperature) since the TPS40060 doesn't have any thermal compensation.

Second, C9 should be populated with a 100pF - 470pF capacitor to help the ILIM pin voltage track the VIN voltage more accurately, remvoing VIN ripple voltage from the current limit sense circuit. This capacitance is necessary due to the parasitic capacitanec of the ESD structure between the ILIM pin voltage and GND.

2. The Inductor L1 is fixed to 10 uH. While calculating using the formula in the data sheet ends up in some wrong value. Kindly review

Using a target 30% peak-peak ripple at full load, I calculate 9.5uH inductance.

In Equation 57 from the datasheet the equation is: (Vin - Vout) x (Vout / Vin) x (1/fsw) x (Ipk-pk) for the design example this is [ (48V - 3.3V) x 3.3V ] / [ 48V x 2.0A x 130kHz ] (2.0A is approximately 0.3 x 7A)

Using your numbers it is [ (36 - 14) x 14 ] / [36 x (0.3 x 10A) x 300kHz ] = 9.5uH

Both Equations are correct, and actually the same, though Equation 57 doesn't show the derivation of the 2A pk-pk ripple current in the inductor.

3. As the present design had a lot of noise at L1 out, we have added a second filtering stage (L6, C29, C30)and we would like to remove it . Kindly comment.

Without insight into the "noise" on the ouptut of L1, it's hard to comment on its source. There is only 2x 1000uF electrolytic capacitors on the output with no ceramic bypass before L6. The output node of L1 likely has a high Equivelant Series Inductance (ESL) and Equivelant Series Resistance (ESR) and is thus likely unable to filter high frequency ripple (triangle wave on the output due to the inductor ripple current across the ESR of the output) and switch-edge transition (square wave on the output due to the output capacitor current changing sign with each switching edge). This noise could be effectively filtered by adding some ceramic capacitance in parallel with C14 and C15. The 2x 1.0uF (C32 and C33) are a good start, but I would recommend something larger, like 2x 4.7uF or 2x 10u.

At 300kHz, each cycle of a 3A pk-pk triangle wave contains 1/2 * (1/2*3A) * 1 / 2*300kHz) = 1.25uC of charge. 2x 1uF would leave almost 600mV capacitive ripple while 2x 10uF ceramic would reduce this to abut 63mV while providing a very low ESR (1-2mOhms) and low ESL. This would likely eliminate the need for L6, C29 and C30.

4. As there was noise coupled to the Vin pin too we have added the filtering cap C1, C2, C3 : 470/50V and C75, C76 : 6.8 u ( Ceramic ones). Kindly comment.

At full load (10A) and low line (18V), the power stage is drawing 10A pulses of current at 78% duty cycle out of the input capacitor for 26uC of charge. Again, the high ESR and ESL of the input capacitors coupled with the high impedance of the source voltage (LF2 = 2mH) produces very high ripple voltage.

Just like the ouptut, the input would really benefit from some additional ceramic input capacitance. The 36V rating of the input can made adding a lot of capacitance difficult, but adding several 10uF input capacitors in parallel will likely be more effective than C1 - C3 (though you'll likely want to keep at least 1 of these bulk capacitors to provide hold-up following a load transient.

The best way to size the ceramic capacitance required at the input of a switch mode power supply is to look at the ESR and RMS current ratings of the bulk hold-up capacitor (the 470uF electroltic capacitors in your case) and size the ceramic capacitors to limit the voltage ripple on these bulk capacitors to 1/2 their Irms rating when the entire ripple voltage is forced across their ESR.

Vin(rip) = sqrt(1 / 12) * 1/2 (Irms * ESR) (RMS of a zero average triangle wave is sqrt (1/12 * pk-pk^2) = sqrt (1/12) * pk-pk )

Cin(cer) = Vin(rip) / [ Iout(max) * Vout ] / [ Vin(min) x fsw ]

0 vsc over 14 years ago in reply to Peter James Miller

Prodigy 45 points

Dear Peter,

Thanks a lot for the kind support you always provide us I have a couple of more question to ask.

Kindly support

1. As per the design example provided with TPS 40060 DATA SHEET , The R1 is 100K and R Bias is 26.7 K. As per the formula for calculation Rbias ( equation 23 ) R1 can be any value . Any significance for the 100 K ?

2. Can you please brief me little more on the purpose of SW NODE resistor ( 10 ohm).

3. Can you please let me know the normal and maximum current handling capacity of the SW node ( Sink)

4. In the design example provided with TPS 40060 DATA SHEET ,The drain pin of upper mosfet is connected to schottky diode, but in our present design it is been removed abd we add 3 ceramic capacitors on the Source pin( inorder to reduce noise) Can you please comment on this

Thanks in advance

0 Peter James Miller over 14 years ago in reply to vsc

TI__Guru 56985 points

No significance to the 100k FB to VOUT resistor. We generally recommend a 10k - 100k value for this resistor. In this case, 100k was selected to minimize current flow from output to FB. In general, as output voltages increase the values of these resistors also increase to reduce current, but it is not necessary. The converter would work in a similar fashion with R1 = 1k and Rbias = 267W

2. Can you please brief me little more on the purpose of SW NODE resistor ( 10 ohm).

Unlike many other controllers that use N-Channel MOSFETs, the TPS40060 and TPS40061 use P-channel MOSFETs, which are driven between the VIN and HDRV pins. As a result, the SW pin is not part of the gate drive and only used as a sense pin for current limit. To reduce noise, improve curent sense and protect the SW pin from negative rigning on the SW node during the turn-off of the high-side FET, a 10W resistor was added between the Switching Node and the SW pin.

3. Can you please let me know the normal and maximum current handling capacity of the SW node ( Sink)

As stated above, the SW pin on the TPS40060 and TPS40061 do not actively drive the SW pin. The sink capability of the node (junction of drain of the two MOSFETs and inductor) is defined by the low-side FET's Rdson and the Inductor DCR. Internal leakages could source current out of the SW pin on the order of a few microamperes.

The 30BQ060 schottky diode from GND to the switching node (Drain of high-side MOSFET) is designed to carry the inductor's current during the "dead-time" between the turn-off of the high-side FET and turn-on of the low-side FET and the dead-time between the turn-off of the low-side FET and the turn-on of the high-side FET. Without this diode, the current flows through the body diode of the low-side FET, which has a larger forward drop than the diode, dissipating more power.

This is not a significant issue at lower currents or lower switching frequencies, but can dissipate a lot of power at high frequency and high current.

Replacing this diode with a capacitor may reduce switch noise, but does so a significant power expense. The power dissipated charging and discharging a capacitor in this location is Vin^2 * C * fsw - Input Voltage Squared times Capacitance times switching frequency. with a 48V input, 300kHz switching frequency 100pF of capacitance dissipates 69mW of power.