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TPS3711: Expected failure mode when exposed to high dv/dt

Will Brown
Intellectual 451 points
Part Number: TPS3711

I have used the TPS3711 in previous designs without issue. In those designs, the TPS3711 was used to monitor internally generated voltage rails, with usually 1ms startup times.

On a present design, one of the TPS3711 parts is powered directly from external power input.  In a lab setting, power was abruptly applied by plugging a banana-lead directly into a power supply that was already on at +28V (GND was connected first, then +28V).  I did not have dv/dt protection on the TPS3711, and the part failed by obliterating its Vdd pin.  The part is fed by a 0.005" trace about 2" long (2 oz copper) and that track was unfazed.  I have more parts on the way to recreate the experiment, and eventually plan to filter Vdd per section 9 in the datasheet.  

I am wondering if the expected failure mode of the TPS3711 when given a Vdd with a dv/dt that exceeds 1V/us is for the part to basically grenade?


Thanks,

Will Brown

  • 0
    Intellectual 451 points

    I also note the R/C values in the datasheet are insufficient to lower the dv/dt below 1V/us for an input of 28V.

  • 0 in reply to Will Brown
    TI__Guru 56345 points

    Hi Will,

    Was there an input capacitor on VIN?  I dont believe 0.01 uF capacitor value represents all slew rate cases of VIN .  Also, where you able to get a scope photo on VIN when you "hot plugged" the banana-lead directly to the power supply?  My guess is that VDD exceeded the abs max rating of 40V and the pin was damaged.  

    The banana-lead cable has inductance and the longer the cable, the more inductance it has.  For this particular case, I would try increasing the input capacitor value to effectively reduce the slew rate so VDD does not exceed the abs max rating.  Also, if you can provide a scope photo of the VDD voltage on the pin, that would be helpful to understand what is happening with your setup. 

    Ben

  • 0 in reply to Ben C
    Intellectual 451 points

    Hi Ben,

    Thanks for the feedback.

    Yes, there is a 0.1uF on the Vdd pin.  Your point is well taken about stray inductance causing interaction and violating abs-max on the part.    The event was not instrumented, as I was just passing the hardware over for a "quick software update" from a developer.  Hence the careless application of power and not monitoring anything at all.  I guess back to my original question, whether I violated 40V, or the 1V/us dv/dt recommended in section 9, was such a catastrophic failure expected?

    Once I get more parts in-hand I will recreate and perform more instrumented testing.


    Will

  • 0 in reply to Will Brown
    TI__Guru 56345 points

    Hi Will,

    Yes, for ICs that are not designed for hot plug events, this phenomenon will most likely will cause a catastrophic failure and is expected.

    Ben  

  • 0 in reply to Ben C
    Intellectual 451 points

    Thanks Ben - I will leave this thread open for now and post my re-testing results for future readers/googlers.

    Will

  • 0 in reply to Will Brown
    TI__Guru 56345 points

    Hi Will,

    Keep me posted!  Thanks,

    Ben

  • 0 in reply to Ben C
    Intellectual 451 points

    Hi Ben,


    With a new part on a test PCB, I cannot recreate the failure.  I recreated the hot-plug situation, and can handily create 50V ringing at Vdd with a few feet of 20awg power lead, and the power supply set to 23V.  I also later remembered that I did some testing of a downstream voltage clamp circuit, and had Vdd exposed (inadvertently) to something like 50V sustained during that period of testing.  I recreated this 50V sustained input to Vdd, and could not get the new part to fail in such a manner.  The fact that the part that failed the other day basically was missing a lead from the package ("vaporized"), but the 5mil PCB trace leading to it was intact, leads me to believe that while I did stress the part beyond abs max ratings, I think it was a bathtub curve sort of failure event.  Pure guessing.

    In the final design I will pick-off Vdd from after my voltage clamp stage, which limits the downstream bus to 30V.

    Thanks for your time,

    Will

  • +1 in reply to Will Brown
    TI__Guru 56345 points

    Hi Will,

    Thanks for the update and I am so glad to hear that your setup is working!  Good luck to you!

    Ben