LM25117: MOSFET and output capacitors failing

Hi Aquiles,

The schematic is a little hard to read. Please check that the inductor is not saturating (the sat current should be well above the peak current limit).

Note you can use the LM25117 quickstart calculator to check compensation (at least for constant Vout operation as a starting point).

Regards,

Tim

Hi Tim, thanks for the comment. Try clicking on the image several times. I can open a high-res image on the page at this time. I'll look into the inductor saturation.

I notice there's no traditional output voltage feedback, so if the current loop doesn't behave properly, it may cause Vout to go high. Also, the MOSFET Miller plateau voltage is quite high, about 5V.

Regards,

Tim

Hi Tim, thanks for the feedback. We are operating the converter only in CC mode, and I have tested the machine to limit output voltage at 22V. It seems it may be beneficial to add an OVP circuit to the VCCDIS pin. I believe this approach would help address the Cout failures.

I am not familiar with the effects of the Miller plateau voltage in buck topology, can you please explain? Is it we could be using the controller close to the HO and LO limits, and not fully turning ON Q1/Q2?

Any feedback is greatly appreciated. 

Aquiles,

We prefer to have a few volts of overdrive given the gate drive amplitude (VCC) relative to the Miller plateau voltage of the FET (the flat line in the Qg vs. Vgs curve in the FET datasheet). This ensures the FET is adequately enhanced when conducting. I noted the BSC066 FET used here is somewhat high (5.2V) for a 60V device - see Fig 14 in that datasheet. But it should still work adequately  with the LM25117's 7.6V gate drive amplitude.

Regards,

Tim

Hi Tim,

Thanks for the clarification. This makes sense, as a partially enhanced FET will have poor conductivity. We are seeing very consistent failure in the Q1, besides adding a dedicated heatsink to that FET, could there be other circuit improvements that could work? Also, failures are occurring at 20-30 hours of service, and with different inductors (15 uH and 33 uH). 

Thanks again and please let me know if you have other recommendations. 

Aquiles,

Maybe check stability via simulation or by looking at transient response, especially given the electrolytic output caps that possibly have high ESR (especially at cold). The power stage looks okay and the inductor is large footprint rated for 12A.

Regards,

Tim

Hi Tim,

Thanks for the ideas. 

No problem, Aquiles.

Regards,

Tim

Hi Tim, we have been testing the conditions that may lead to the Q1/MOSFET failures. We wanted to consult with you to see if there is some merit to our ideas.

In particular, we noticed that when the LM25117 detects a short-circuit condition, the Q1 Vgs is driven at approximately 1.3 V in our circuit. Although output voltage is very low (~130 mV), and current is 0, we think that these particular conditions lead to the MOSFET failing prematurely:

1. The machine detects open circuit/short circuit. HO/LO are shut down.
2. Using oscilloscope we measure HO-SW voltage to be around 1.3V.
3. In our design, the Q1 MOSFET has Vgsth of 2.8V.
4. These conditions cause the Q1 MOSFET to be partially conducting, leading to high Rds(on). 
5. 24 V still applied across Q1, leading to power dissipation (small?) on Q1 due to high Rds(on). 
6. Q1 fails prematurely under these conditions.

Does this thinking make sense? Any feedback is appreciated. 

Hi Aquiles,

The HO to SW voltage should be 0V when the FET is off as there is an active pulldown. Please ensure you are making a differential measurement from HO to SW.

Even if a voltage of 1.3V is present, it shouldn't cause the FET to conduct.

Regards,

Tim

Hi Tim, here are 2 oscilloscope measurements when the circuit was under a fault condition, HO:

SW:

Any issues here?