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LDO5P0 of TPS6508640RSKT abnormal power down

li xue
Prodigy 70 points

The shape of LDO5P0 is as follows,Why does this happen？

  • TI__Genius 17380 points

    Hello,

    LDO5P0 is enabled and disabled based on VSYS_UVLO_5V from the specification - namely VSYS falling below 5.4V nominal will cause LDO5P0 to turn off. 

    Alternatively, if current draw was exceeding the current limit (200 mA), then the voltage would drop.

    I have seen waveforms like above in the past, it is not generally unexpected. If the input supply is dying while PMIC is drawing significant current, then hitting UVLO will cause the PMIC to shut down. This often lets the input supply recover slightly, re-enabling the PMIC until the input supply droops again below UVLO. You can take a look at the VSYS pin voltage at the same time to confirm. If VSYS is stable above 6V, then I would check if there is something attached to LDO5P0 that should not be.