This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS50601A-SP: Issues testing sync on the evaluation board

Part Number: TPS50601A-SP
Other Parts Discussed in Thread: TPS50601ASPEVM-S

We purchased the eval board:  TPS50601ASPEVM-S... during testing, we have had issues with introducing interrupts to the sync signal in various forms and all of them not re-synching when we re-establish the connection.  Can you tell me a few things about the eval board:  1) can I populate the top section to perform testing on a functional circuit.... 2) anything I need to do to the original circuit to not have it interfere with the new populated section? How should the sync signal be applied to the circuit, does it involve the un-populated U3 and U4 (SLHR003 rev C)?

  • Hi,

    When you mention 'introducing interrupts' I assume you are referring to an externally supplied clock being interrupted. To inject an external clock you must install the DNI'd components J18, R46, R51, R45, R41, R7 and then provide your external clock signal to J18.  U3 and U4 are only needed if parallel operation is required.  But you mention you purchased a 1-CH EVM so I don't think you would need U3 and U4 unless I'm not understanding something here.  Let me know if this helps.

    Thanks

    Christian

  • Yes, we purchased the 1-CH EVM, but populated our own design on the top section.  Our full design will run two of the TI chips in Buck configurations from 1 source, but each output will have different voltages.  Their outputs will be providing power to different loads. Can we still use the method discussed above and not need the U3/U4?

  • Since the devices are not actually in parallel, i.e. output voltages not tied together and output currents not summed to one node, there is no need to phase shift the clock phases between the two converters.  You can use the external supplied clock to both DUTs via J18 connector- you just need to populate the DNI'd components to the 2nd DUT now so the clock reaches the SYNC pin.  Note, in your system, you must ensure that your clock source has sufficient drive to meet the signal integrity requirements of the SYNC input pins.  

    Thanks

    Christian