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Original question:

TPS650864: tps650864

TPS650864: Power Up Sequence Control by CTL Pins

Teik Hooi Teoh
Intellectual 655 points
Part Number: TPS650864
Other Parts Discussed in Thread: TPS650861

Hi,

I would like to understand further on the CTL pins for the bootup sequence in TPS65086401.

FPGA device to be powered is Xilinx Zynq Ultrascale+ ZU3CG.

The power up sequence is described in Figure 8-7 of the TPS650864 datasheet.

  1. So should only the CTL1, CTL6 and CTL4 pulled up to 1.8V rail?
  2. CTL3 = 1 (pull up to 1.8V), CTL2 = 0 (pull down to GND) for BUCK6 output  = 1.2V?
  3. This 1.8V rail should be available in the system before all the outputs from the PMIC are enabled?
  4. Or should there be any control sequence of external signals connecting to CTL1/6/4 pins to enable the power up sequence stated in Figure 8-7?
  5. If not used, for example CTL4, they should be pulled to GND? In this case, will BUCK3, LDOA3, SWB1_2 and BUCK5 enabled?
  6. If CTl1 is pulled to GND, does it mean all the subsequent power up sequence of PMIC outputs will all be disabled (except for LDO5 and LDO3P3)?

Regards,

  • 0
    TI__Genius 17380 points

    Hello,

    Thank you for reaching out - I have added my notes to the questions below:

    1. So should only the CTL1, CTL6 and CTL4 pulled up to 1.8V rail?
      1. [KL] It depends what you would like the PMIC to do. Every Ultrascale+ use is different so the PMIC has some ability to be flexible to your needs. Commonly, CTL1 is tied to LDO3P3, CTL6 is connected to GPO1, and CTL4 is GND if the extra rails are not needed (or can be enabled by I2C after boot up). Generally there is not a 1.8V rail available until BUCK1 is enabled so the 3.3V is used instead. The CTL pins accept 3.3V as well.
    2. CTL3 = 1 (pull up to 1.8V), CTL2 = 0 (pull down to GND) for BUCK6 output  = 1.2V?
      1. [KL] Correct, though CTL3 can also be tied to LDO3P3 if that's easier.
    3. This 1.8V rail should be available in the system before all the outputs from the PMIC are enabled?
      1. [KL] CTL2 and CTL3 would just need to be set by 2 ms after BUCK1_PG based on the sequence, so they could use BUCK1, or LDO3P3.
    4. Or should there be any control sequence of external signals connecting to CTL1/6/4 pins to enable the power up sequence stated in Figure 8-7?
      1. [KL] CTL1 sometimes has control logic in front of it (push button - https://www.ti.com/lit/scea048 for example), but often enough it's just tied to LDO3P3 as long as the intent is to be always on.
    5. If not used, for example CTL4, they should be pulled to GND? In this case, will BUCK3, LDOA3, SWB1_2 and BUCK5 enabled?
      1. [KL] Correct they can be tied to GND, and in that case they would not be enabled. They can be enabled by I2C if desired.
    6. If CTl1 is pulled to GND, does it mean all the subsequent power up sequence of PMIC outputs will all be disabled (except for LDO5 and LDO3P3)?
      1. [KL] Correct - if you wanted to look at the power good tree for this device you can check out https://www.ti.com/lit/zip/swcc026 
  • 0 in reply to Kevin LaRosa
    Intellectual 655 points

    Hi Kevin,

    Thanks for the helpful information.

    Regarding the delay to be added to CTL: how do we add those delays? Will the settings be stored in the OTP or every power up need to be re-configured?

    Looking at the power up requirements of the Xilinx Zynq Ultrascale+ datasheet:

    For the PS domain:

    To achieve minimum current draw and ensure that the I/Os are 3-stated at power-on, the recommended power on sequence for the low-power domain (LPD) is listed:

    1. VCC_PSINTLP
    2. VCC_PSAUX, VCC_PSADC, and VCC_PSPLL in any order or simultaneously.
    3. VCCO_PSIO

    However, according to the TPS65086401 reference connection and the power up sequence (in TPS650864 datasheet):

    It looks like the VCCO_PSIO (if supplied by BUCK1 1.8V output) will be at the same time as VCC_PSAUX, VCC_PSADC and VCC_PSPLL.

    Is this contradicting to the requirements of FPGA device?

  • 0 in reply to Teik Hooi Teoh
    TI__Genius 17380 points

    Hello,

    I am not sure what CTL delays you are discussing. If you want to modify start-up and shut-down delays from the default, the TPS650861 would need to be used.

    As far as the timing, you are correct that there may be some additional power draw during the power up sequence if VCCO_PSIO is merged with VCCAUX vs. full power separation. Use of the TPS650861 can optimize to your particular setup, or I2C voltage setting and enabling/disabling could be used for one of the other regulators like BUCK3 if desired.