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Hi Teams
I am assisting customer to design with UCC28740 and have few questions about its control law.
Based on the control law shown in datasheet, the primary peak current and frequency is depenons on the Vcl, which is generated by the current flow into FB pin.
Lower FB current lead to higher Vcl indicate heavier load in output side.
The feedback pin current decrease means the current flow throungh the opto-coupler is decrease either.
I not fully understand how the secondary feedback network to adjust the current flow through the opto-coupler during heavy load condition. Is it a fixed voltage error is needed to generate such current?
Hi Gabriel ,
As load increasing , the output voltage will a little lower than regulation voltage, there is a error amplifier in the 431(shown in below image left side), the internal error amplifier will increase the impedance of 431's CATHODE pin , then in Iopt will decreasing (shown in below image right side ). in this way , the out load will influence the primary side IFB current. Hope this can answer your question. Thanks.
Hi Jaden
Your answer is very clear. Thanks. One more questions about the driver capability:
Based on internal system block diagram,UCC28740 gate driver is implement a constant current source in DRV pin during on-time.
So the peak current output of this driver is only 25mA?
Most of gate driver I have seem is constant voltage type, why UCC28740 select constant current type? What's the major advantage?
In the meantime 25mA driver capbality seems not ensure to achieve fast turn-on and off the MOSFET, some reference design add external
transistor to enhance driver capability. Any guideline about in what condition we need external transistor circuit for the MOSFET?
