TPSM846C24: No output in parallel mode

Leon Ni 

A couple of things to check:

1) Is the SYNC input to both devices switching?  In a stacked configuration, the TPSM846C24 requires a SYNC input to the secondary device to track the switching between the two devices.  Without a SYNC input, the device will declare a fault and will not generate an output.

2) Are the modules not generating an out, or are they attempting to start-up and repeatedly shutting down due to a fault condition?  You can measure the VSHARE voltage to determine.  If the parts are in shut-down, the VSHARE voltage will remain low, held below 0.2V.  If the parts are repeatedly trying to restart, VSHARE will be held low with periodic rises was the parts attempt to start, detect a fault, and then shutdown.

3) The schematic's output capacitance does not appear to meet the minimum recommended output capacitance, which is 2x 470uF electrolytic capacitors + 4x 47uF ceramic capacitors per TPSM846C24.  If you are seeing repeated start attempts, the output may be triggering OV or UV faults due to the low output capacitance.

The lack of ceramic capacitance is likely amplified by J26 - J29 between the output of the TPSM846C24 modules and the ceramic capacitors, adding additional impedance to the loop before the high-frequency bypass capacitors and the output.

Dear, Peter

Thank you very much for supporting.

1. For sync signal, there is Y9 and U44 to offer both Master and Slaver TPSM846C24 500KHz frequency.

2. I have checked VSHARE signal, there is periodic rise, like the picture shows below. It indicated that DCDC is trying to restart.

3. For capacitance, I add extra 6pcs 470uF Tantalum capacitors (total 8pcs Tantalum capacitors), extra 6pcs 47uF Ceramic capacitors (total 8pcs Ceramic capacitors), like the picture below: Still no working. 

BTW, there are more decoupling capacitors under the loading (FPGA).

4. I also change R230 to 499Ohm, C367 to 2.2nF to meet spec, still no working.

Brs,

Leon

Here is the detail picture of VSHARE：

Leon Ni 

Am I reading your oscilloscope waveform correctly that VSHARE is rising from 0V to approximately 4.8V, then dropping to approximately 2V before being discharged to approximately 0V all in 1us?

Can you check the VIN and VINBP pin voltages to see if they are dropping out, as well as the VCC_VCCP_EN input from PG1_EN to make sure that the EN pin is not being pulled low to turn off the output? 

The schematic only shows 2x 10uF bypass capacitors for the two TPSM846C24 modules, but askes for a minimum of 4x22 or 2x 47uF.

The VSHARE waveform indicates that the parts are trying to startup, but are triggering a shutdown almost immediately.

Dear, Peter

You read the right VSHARE waveform.

There is one strange thing:

That I remove the R228 and R231, separate the net "VCC_VCCP_EN" alone, away from other net. Just Master and Slaver EN pin is connected.

The voltage of "VCC_VCCP_EN" is 6V4, and the VSHARE has the same above waveform. After I short "VCC_VCCP_EN" to GND, the DCDC goes into shutdown mode, VSHARE has no waveform, returns to 0.

That's very strange, if EN pin has default voltage (6V4), why datasheet says that it has the typical voltage 3V3, and suggest to connect to BP3 power rail by 10K resistor?

BTW, I have checked 12V VIN and Enable signal, neither of them is dropped below the threshold.

As to input capacitors, there are plenty of them on the board, they are not displayed in the schematic.

Leon Ni 

The EN pin has a weak internal pull-up to BP6, so it will pull-up close to 6.5V when unloaded. 

The recommended operating conditions recommend driving the pin with 3.3V logic and the 10k pull-up to BP3 limits the leakage current from BP6 into BP3.

Leon Ni 

Thank you for checking, I am still looking into what could be causing the parts to attempt to start-up and shut-down so quickly.

The TPSM846C24 draws short duration, high current pulses of energy from the input at the 500kHz switching frequency.  It is important that the minimum input bypass capacitance is met close to the IC as parasitic inductance between the VIN input and the bypass capacitance can limit the ability of capacitors further away from the module to deliver this energy to the module.

Dear, Peter

I have tried that after removing Slaver TPSM846C24, Master DCDC can generate right output.

Leon Ni 

Thank you Leon, that was what I was going to ask you to try this morning.

That means that device 1 (Slaver) is holding the rail off when device 0 (Master) is trying to start-up.  There are  not allot of reasons Device 1 would shutdown.

One thing I just thought about.  What is the timing between the start of the 12V input and 3.3V standby?  Normally, we recommend the FB pin of Device 1 be pulled up to it's BP3V, and your schematic has it pulled up to 3.3V Standby.  This could present a start-up timing sequence issue if 3.3V Standby is not available when VIN reaches UVLO release threshold.  The Module could power up in Single Phase mode, and then declare an OV when FB is pulled to 3.3V.   Since you have Device 1 removed, check the FB pin voltage during a power-up sequence with just Device 0 installed and see the timing between FB being pulled up to 3.3V and the 12V reaching 4V.

As a rule, it it better to have FB pulled to BP3 rather than a separate 3.3V that might have different start-up timing.

1) VIN below UVLO.  The best way to check this is to measure the VINBP and BP6 voltages, if VINBP is 12V and BP6 is 6.5V, VIN is above it's UVLO and that is not why device 1 is shutdown.

2) Enable Low.  The best way to check this is to measure the EN voltage, it should be above 1.3V

3) Over Current.  Device 1 can not declare an overcurrent without switching, and can not declare overcurrent within 1us of starting switching, so it should not be overcurrent.

6) SYNC.  Device 1 requires an external SYNC to enable its output, and the SYNC must be within +/- 20% of the RT programmed switching frequency.  If it does not receive an external SYNC signal, it will prevent Device 0 from starting up.

Since you have Device 1 removed from the board and Device 0 working, check:

1) SYNC signal at the Device 1 SYNC pin pad to make sure it is getting a valid SYNC signal

2) RT_SEL resistance to ground, this should be shorted to ground, but it's worth double checking.

3) Swap Device 0 and Device 1 so that your original Device 1 is populated in the Device 0 location and Device 1 is unpopulated.  Does the original Device 1 work as a single-phase design when populated in the Device 0 location?

5) Over Temperature.  Device 1 has an internal temperature sensor and will prevent start-up.  When you try swapping Device 1 into the Device 0 position in step 3 above, if Device 1 does not work in the Device 0 location, it could be a faulty temperature sensor.

Leon Ni 

I am glad we were able to find the problem and address your issue.  I am going to close this thread.  If you have additional questions, please start a new question thread.