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LM7480-Q1: LM74800

Massimiliano Di Ruggiero
Prodigy 45 points
Part Number: LM7480-Q1
Other Parts Discussed in Thread: LM7480, LM74800-Q1

Dear Team, 

would You check if the schematic is suitable for the following requirements?

  1. VIn: 4,5-36V
  2. Max output current: 1,3A
  3. 1 minute at 42V
  4. ISO 7637-2:2011 Pulse 1:
    -600V
    Ri = 50 Ohm
  5. ISO 7637-2:2011 Pulse 2a:
    +50V
    Ri = 2 Ohm
  6. ISO 7637-2:2011 Pulse 2b
    +20V
    Ri = 0,05 Ohm
  7. ISO 7637-2:2011 Pulse 3a
    -200V
    Ri = 50 Ohm
  8. ISO 7637-2:2011 Pulse 3b
    +200V
    Ri = 50 Ohm
  9. ISO 16750-2:2012 Pulsa 5a (Load dump)
    +174V
    Ri = 2 Ohm

The circuit should limit the output voltage to 40V during the 42V input test too.

Thank You in advanceLM7480.pdf

  • 0
    TI__Guru** 105361 points

    Hi Massimiliano,

    Thanks for reaching out!

    We will review and get back by early next week.

    Best Regards, Rakesh

  • 0
    TI__Guru 57737 points

    Hi Massimiliano,

     

    Please see my comments below,

    1. ISO 7637-2 Pulse 1 needs to be clamped on the negative side by the TVS. The TVS you have selected will work for Pulse 1 but they may not be suitable for 200V load dump which is generally there for longer durations like 350 ms. A combination of SMBJ150A + SMBJ33CA in series can be used as shown in datasheet. For more understanding on TVS selection, please refer to 'SMBJ150A for D3 and SMBJ33CA' section of the datasheet.
    2. LM74800-Q1 is rated for 65V , so it can withstand pulse 2A and 2b comfortably. 
    3. ISO 7637-2 Pulse 3A and 3B are  very fast repetitive pulse of 200 V 100 ns that are usually absorbed by the input and output ceramic capacitors.
    4. You have connected OV pin to Output to achieve OV clamp. In OV clamp operation, the FET will be stressed due to power loss ((Vin-Vout)*Iout) in it. In this case the power loss would be ((42-40)*1.3) = 2.6W. Please check if the BSZ900N2 can withstand this power across it for 1 min. This would be a big challenge for the FET.
      1. To avoid stress on the FET, you can connect the OV pin to the Input side to configure as OV cut-of. In this configuration, there will be no power stress on the FET as the FET will be turned OFF when Vin rises above OV threshold (say 40V). See Figure 10-27 in datasheet. 
    5. For R1 and D5 power rating, please refer to '10.3.2.3 VS Capacitance, Resistor and Zener Clamp' section of the datasheet.
  • 0 in reply to Praveen GD
    Prodigy 45 points

    Hi Praveen, thank You for your support!

    I added some detail in the schematics:

    LM7480_V2.pdf

    1. I have to limit the voltage to 65V because of other electronics connected to the supply. If a single SM8S36CA is not enough, I will check for a couple of SM8S18CA in series. Note the internal resistance of the load dump generator is 2 Ohm.
    2. Ok
    3. Ok
    4. Sorry, I've not explained: 1.3A is on 6V output, thus @ 40V should be something below 250mA (supposing an 80% of efficiency of DC/DC converter). The power dissipation on the mosfet should be ((42-40)*0.25)=0,5W. 
      1. I can't switch off the mosfet during load dump as the circuit must work during load dump, thus I need the clamping feature of the LM74800
    5. I added D4 to extend the lower voltage limit of the circuit as low as possible using the buck/boost DC/DC that can works down to 2.7V. Then I added R1, D1.
      D5 is an addictional protection, but should not be necessary if the input voltage is limited to 65V. 
  • 0 in reply to Massimiliano Di Ruggiero
    TI__Guru 57737 points

    Hi Massimiliano,

    Thanks for sharing more information. I will get back to you soon.

  • 0 in reply to Praveen GD
    TI__Guru 57737 points

    Hi Massimiliano,

    Please see my response below,

    1. Yes, the load dump generator has an internal impedance of 2 ohms but the duration of load dump is too high - 350ms, which is almost like a DC condition. So, it is advisable to select a TVS with breakdown voltage > Max load dump voltage. In case you want to clamp the input voltage during load dump, you need to select a TVS which can withstand Power = {[(Load dump voltage - Clamping Voltage)/2] x [Clamping voltage]} for 350ms across it.

    In any case the Common Source topology will clamp its output voltage to a value set by the OV pin. So, the load dump at the input will not be seen at the output due to the OV clamp feature. So, you need not clamp the input voltage using a TVS. 

    4. A power dissipation of 0.5W should not be a challenge for the FET to handle. But please check the FET temperature rise (dependent on Ambient temperature, RQJA of FET on your board) and the FET SOA (how much current can the FET handle for DC condition with 2V across it).

    5. Yes, the LM74800-Q1 can work as low as 3V on the VS pin. It is true that as long as the voltage on VS is limited to <65V, the D5 is not necessary but that is not the case during Load dump (assuming you have chosen the input TVS breakdown voltage to > Load dump voltage) .