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BQ79616-Q1: external balancing mosfet configuration

luca buccolini
Prodigy 130 points
Part Number: BQ79616-Q1
Other Parts Discussed in Thread: BQ79616,

Dear TI support,

I'm going to use the BQ79616 with external mosfets as we need high balancing currents but we have some doubt based on the (SLVAE87 – FEBRUARY 2019) document:

  1. Are there any app. note / EVB that describes the values used in the Figure 4-5 ?
  2. The document report: "The VDS must be selected based on derating requirements determined by the stack voltage.".
    1. You mean the full stack voltage? Why? The MOSFET is connected, neglecting the series resistance RexBAL, across the cell that is <5V.
  3. What is the purpose of R_DIS (optional)?
  4. What is the purpose and the typical value of C_HP ?

Thanks in advance

Best regards

  • 0
    TI__Prodigy 160 points

    Good evening Luca,

    We do not have an app note/ EVB referencing the values described in Fig. 4.5. In order to reply to your queries, I will perform internal searching and gather your answers and send the requested information tomorrow. Please note that it will be treated with the upmost sense of urgency.

    Best Regards,

    Christian Ammon

  • 0
    TI__Prodigy 160 points

    Good day Luca,

     

    We appreciate and thank you for your patience. With regard to your queries, please see below:

    1. There exists no current app note/ EVB pertaining the values referenced in Fig. 4-5 of the Design Recommendation document for the BQ79616-Q1 device.

    2. The full stack voltage refers to the voltage from across the top of the battery stack to ground (BAT to GND). The full stack voltage controls the expected cell voltage per channel, driving VDS in the FET. For example, should you use a full stack voltage of 80V, 5V*16 channels, you will require a different VDS value for each FET than if you had a 48V stack, 4V*16 channels.

    3. R_DIS is chosen to discharge the high pass/ hot plug capacitor.

    4. C_HP refers to the high pass/ hot plug capacitor.

    In general, we encourage customers to employ use of internal cell balancing as it strays from the recommended schematic. When performing external cell balancing, circuit design depends on needs of the consumers. Therefore, the values of R_DIS and C_HP will depend on your requirements.

     

    Best Regards,

    Christian Ammon

  • 0 in reply to Christian Ammon
    Prodigy 130 points

    So, referring to the point 2, are correct the following assumption?

    If I use a full stack voltage of 80V (5V*16ch) I have to use a balancing mosfet with a minimum Vds_MAX of 5V (+ derating).
    If I use a full stack voltage of 64V (4V*16ch) I have to use a balancing mosfet with a minimum Vds_MAX of 4V (+ derating).

  • +1 in reply to luca buccolini
    TI__Prodigy 160 points

    Good day Luca,

    Yes, your assumptions are correct. The expected cell voltage per channel guides the VDS spec in the FET.

    Regards,

    Christian Ammon