• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 216 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PFC Design

Sam Ref
Expert 1610 points

Hello,

We are implementing TIDM-2008 (Bidirectional Interleaved CCM Totem Pole Bridgeless PFC Reference Design Using C2000Tm MCU). Questions are;

  • In PFC mode DC Bus Control; the reference .pdf of that design shows (Labs 3 & 4 and Figure 2.9) that we can control current to cope with load changes. That document also shows (Figure 2.11) that the output DC voltage can be controlled/regulated while maintaining low-bandwidth response (~10 Hz). What is the permissible range of that DC voltage change? Can we take that DC voltage to say 5% of the input AC voltage? If not, what is the barrier?
  • Number of switches. We can use only 4 power switches (GaN , MOSFET or SicMOSFET) to realize DC volt control and PFC of single-phase AC input. Correct? In your reference design you use 8 power switches (6 GaN switches and 2 MOSFETs) all to realize interleaving and reduce the ripple. Correct?
  • Three-Phase PFC. Does Texas Instruments have an explicit three-phase PFC reference design that uses 6 power switches? Vienna configuration is not justified in our case.

Regards

Sam Refaat

  • 0
    TI__Genius 11815 points
    • In PFC mode DC Bus Control; the reference .pdf of that design shows (Labs 3 & 4 and Figure 2.9) that we can control current to cope with load changes. That document also shows (Figure 2.11) that the output DC voltage can be controlled/regulated while maintaining low-bandwidth response (~10 Hz). What is the permissible range of that DC voltage change? Can we take that DC voltage to say 5% of the input AC voltage? If not, what is the barrier?

    Figure 3-61 shows this DC voltage change under transient. Voltage Transient With Non-Linear Voltage Loop, Vin 120 Vrms, 880 W to 0 W Transient, Overshoot 16.8 V.

    So this is about 4% of the rated DC bus voltage (400V)

    • Number of switches. We can use only 4 power switches (GaN , MOSFET or SicMOSFET) to realize DC volt control and PFC of single-phase AC input. Correct? 

    The one we implemented is a Totem-Pole PFC with 3 interleaved phases. With 4 switches you can also implement a TP PFC with no interleaving. That will be a single inductor TP PFC design.

    • In your reference design you use 8 power switches (6 GaN switches and 2 MOSFETs) all to realize interleaving and reduce the ripple. Correct? 

    Yes, 6 GaN switches are for 3 interleaved phases. 2 Si MOSFETs switch only at the line frequency (50 or 60Hz)

    We dont have a 6 switch 3phase PFC design at this time. We have TIDA-1606 which implements a 3Ph T-Type multi-level PFC.

    Shamim