TPS2388: Tpdc timing fail via Sifos testing

Eric Fang1

Intellectual 620 points

Part Number: TPS2388

Dears,

We check Sifos test item and showing Class_Time_Tpdc = 4.9 ms it's less than spec define minimum 5.6ms.

Do we have any way to fix this problem?

Eric

over 4 years ago

0 Darwin Fernandez over 4 years ago

TI__Mastermind 41780 points

Hi Eric, the datasheet specs this timing as a minimum of 6.5ms. Also, when I look at the SIFOS report on the TPS2388 product page, it shows ~10ms.

Are you testing with the TPS2388EVM or your own application circuit? Also, are you using the latest SIFOS equipment and version of the conformance test suite? Thanks!

0 Eric Fang1 over 4 years ago in reply to Darwin Fernandez

Intellectual 620 points

Hi Fernandez,

I think our test result was 4.9ms it's fail relative to 5.6 and 6.5ms, the latest SIFOS spec was Nov 5, 2020?

I testing with the our application circuit, currently SIFOS vesion is 5.2.00.

Eric

0 Darwin Fernandez over 4 years ago in reply to Eric Fang1

TI__Mastermind 41780 points

Hi Eric, looks like you're using the latest BT SIFOS equipment. Can you help attach the SIFOS CTS report so I can see the specific line item failure. Also can you send the schematic of your design for review? Thanks!

0 Eric Fang1 over 4 years ago in reply to Darwin Fernandez

Intellectual 620 points

Hi Fernandez,

Please see the attached file, the schematic was use hierarchical design.

Eric

TPS2388_test report and schematic.zip

0 Darwin Fernandez over 4 years ago in reply to Eric Fang1

TI__Mastermind 41780 points

Hi Eric, thanks for attaching. The only thing that catches my eye is the DNP short from ground to ksense. Just checking that these should be populated on your board, can you confirm? Also what does your power up rails look like? For example, when you first startup the PSE, what does VDD,VPWR, and RESET waveforms look like in one waveform image? Note for initial power up, RESET should be held LOW during power up of the VDD and VPWR rails.

0 Eric Fang1 over 4 years ago in reply to Darwin Fernandez

Intellectual 620 points

Hi Fernandez,

Yes, DNP short was short pad place on PCB.

Can you share the typical power up sequence timing? will it according the af or at mode to be change?

Does the power up sequence will impact the Tpdc timing?

Eric

0 Darwin Fernandez over 4 years ago in reply to Eric Fang1

TI__Mastermind 41780 points

Hi Eric, there is no specific timing between the rails. Only the RESET pin should be LOW while VDD and VPWR rails initially ramp up past their UVLO before the RESET pin can be released. This is to ensure the digital circuits powers up to a known state (like with any IC that contains both digital and analog interacting circuits). I would like to verify this first on your application circuit. Thanks!

0 Eric Fang1 over 4 years ago in reply to Darwin Fernandez

Intellectual 620 points

Hi Fernandez,

Sorry for reply later, I think we find the root cause for this due to power noise.

I will close this case as soon.

Eric

0 Darwin Fernandez over 4 years ago in reply to Eric Fang1

TI__Mastermind 41780 points

Thanks for confirming Eric! How did you solve this issue? Was it at VPWR or VDD rails? Thanks!

0 Eric Fang1 over 4 years ago in reply to Darwin Fernandez

Intellectual 620 points

Hi Fernandez,

The other E2E forum remind we have power noise on Sifos testing.

The strange thing is we change another PSU then we fixed all fail test item.

So I think may PSU impact the test result, if we have new info I will rasie a new forum.

Eric

0 Darwin Fernandez over 4 years ago in reply to Eric Fang1

TI__Mastermind 41780 points

No problem thanks for your inputs! This will greatly help future engineers who may see similar behaviors. Thanks!

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TPS2388: Tpdc timing fail via Sifos testing