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TLV62568: Buck/Pass-through design

Part Number: TLV62568


We are considering using the TLV62568/TLV62568A in a design where the input is 3.1 - 3.5V and the output is 3.3V. It is acceptable to pass-through the input when it is below 3.3V+ dropout.

When I try to do webench design using 3.5V as input (both min and max  = 3.5V) and 3.3V as output, it does produce a design for the TLV62568A, but not for the TLV62568, for which I get the message that a design could not be created.

As far as I can see from the datasheets the TLV62568 and TLV62568A are identical, except the latter is forced PWM whereas the former has a power save mode for low load, so it seems it should be possible to use either.

Is there a reason why the Webench does not provide a design from the TLV62568? Are there are other issues to consider?


Best regards,


  • Hi Anand,

    TLV62568A comes in a DRL package (SOT563-6) & TLV62568 (by default in Webench) is DBV package (SOT23-5).

    For Iout < 1A; SOT563 has the best efficiency. Please refer to the below App note for a better understanding.

    You will also see this efficiency differences in the Webench simulations. But remember to choose the same passives and same test conditions.

    Also, if you calculate Vin_min, for TLV62568A~3.43V & for TLV62568~3.5V and considering the efficiency differences between these two devices, it is clear that TLV62568 requires a higher Vin to deliver 3.3 Vout at full load.

    I hope this helps!



  • Hi Anand,

    Do you have further questions? If not, I will go ahead and close this thread. 

    Please hit Resolved if you agree.