BQ76940: Design Review for BMS solution

Hi Rohsik,

1) It looks like your schematic may have been started with a plan for high side switching.

1. The SMBUS connector J5 includes GND.  Check that this is suitable for your battery architecture and system requirements.  GND will bypass the sense resistor and protection FETs  if J5 and PACK+ are both accessible outside your system
2. J4 includes PACK-, but the other signals are referenced to GND.  These may not work properly, and may cause leakage currents for the battery or damage to the ICs if connected.  For high side switching this should be appropriate.
3. The I2C connector J2 should be for debug only.  No connection is expected on the bus other than the gauge and monitor.  The gauge does not arbitrate for the bus, and if it finds any changes in the monitor settings it did not make it changes them back and may go into a recovery mode.
4. For low side protection FETs the PACK+ and C_15 should be essentially the same point so the Q1 switch with divider to VAUX is basically redundant to the Q3 switch with divider to the BAT pin. That may be desired for confidence checking.
5. The BOOT CIRCUIT seems to be setup for high side switching.  For low side use something more like figure 5 of the slua769 apnote you mentioned.  Figure 5 is DC coupled, you may want it AC coupled like C5, R26 and D12 of your schematic substituting for R5 and D2 of figure 5.  WAKEUP could be a large value pull up to PACK+, but it is a leakage path on the battery if it is continuously attached.
6. It is preferred to have the bottom of C14 connect to GND as shown in the data sheet rather than VC0 shown in several of the application reports.
7. The bottom of C16 should connect to VC5X rather than VC5B
8. The bottom of C15 should connect to VC10X rather than VC10B
9. When using a cell connector such as J14, some users have found it useful to have zener diodes on VC11 and VC6 as shown in figure 21 of the application note https://www.ti.com/lit/pdf/slua749 See the related discussion
10. Be sure your temp sensors or some substitute is connected at J7 during board test.
11. Your FETs seem positioned for high side switching Q26, Q27, Q28 would be the discharge FETs for low side switching
12. R99 should connect to DSG.  The R99 value should likely be 100 ohm minimum. R100, R101, R105 should be small to keep the FETs switching as closely to the same time as possible but large enough to avoid any oscillation at switching.
13. Q33 source should go to CHG.
14. The left side of the precharge resistors R102 should likely connect to the common drain point of the power FETs so that the precharge path is protected from discharge.
15. Check that Q5 works as desired.  We commonly recommend a PNP at this position as shown in the EVM.

2) For low side you will need something more like figure 5.  See note above.

3) Low side switching has the communication interfaces and signals bypass the protection FETs.  In some systems the signals may route to different locations and be considered OK, in other systems it may be unacceptable.  Common solutions are isolation in the communication & signaling paths or high side switching. 

Hello WM5295,

Thank you for the design review and feedbacks, it was really helpful.