Hi team,
customer try to read LP8860-Q1 reg via I2C, sometimes will report NACK and fail to read it.
the signals of below pictures from up to down are LP8860 SDA; LP8860 SCL; SOC SCL and SOC SDA. SOC is mater to read LP8860-Q1.
You can see that, at the 9 SCL, the SDA of LP8860 is high no NACK. but the master pull on the SDA at 9 SCL sent ACK.
have confirm that the power sequence is meet requirement, VDD power on then, power on VDDIO/EN, delay 100ms to read LP8860-Q1 reg.
any suggestions? thanks
