The below picture is from reference schematic. I want to understand why portion covered in red circle is used. It is on DSG pin.
Thanks
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
The below picture is from reference schematic. I want to understand why portion covered in red circle is used. It is on DSG pin.
Thanks
Hi Nitin,
Q29 is a reverse voltage clamp transistor to keep the power transistors off when a reversed charger is connected. See section 2 of the application report https://www.ti.com/lit/pdf/sluaa09 for an explanation. You might check the documentation with the reference schematic however to see if reverse charge was tested. Often the series resistor (R132, R133) to the gate is large due to power dissipation during the reverse charge, and the resistor R134 is small since the gate will have a voltage from the divider with R132, R133, R134 during the reverse charge condition. For reverse charge D37 might be omitted so that the ratio is small. Without D37 when the FETs are on the voltage from DSG will be divided between R131 and R129 (and others), but most will go to the gates. With D37 more voltage goes to the gates and turn on is faster.
Q28 is a turn off transistor for the gates, it provides a local current loop for the gate discharge current from the power FETs rather than the full current needing to return through the IC. The DSG pin provides only the control voltage for Q28 through the large resistor R129. The FETs turn off through Q28 and R135. There is also some discussion in the application report noted, figure 4-2 in the report uses PNP transistors rather than P-ch FETs. Either can work, the P-ch FET has the advantage of voltage control.
Thanks for detailed reply.
Can we avoid to use local current loop Q28 circuit? I see in Application report - Local return current loop is even used for CHG pin when there are 12 power FETs.
If there are lesser FETs, say 3 or less, is it safer to go without local return loops ?
Also It is surprising to know that return current is not good for IC. During Power FET turn on, the same current is coming OUT from IC.
Hi Nitin,
Each additional FET adds capacitance and will slow switching. The part will have a fixed internal resistance and non-linear drive characteristic to meet the timing specifications with the minimum external gate resistance. So more FETs will slow switching and current can't be increased internally. You can switch as many FETs as desired with the internal drive, but at some point the speed may not be acceptable, that is something you must evaluate. 3 FETs may be very suitable with the internal current path. Of course realize that 3 FETs with 4 nF Ciss will be faster than 3 FETs with 10 nF Ciss.