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LM5069: NA

Part Number: LM5069
Other Parts Discussed in Thread: CSD19536KTT

Hi,

We are using LM5069 on one of our power module.

The may reason for the usage of the LM5069 is to get the Supply enable/disable control, Output short circuit protection and also protection against the inrush current.

I have attached the design parameters for your reference.

Note: This is the typical dv/dt rate, but max value can be 1.4x. This is because the gate source current can vary from 16uA to 22uA. Thus TI recommends keeping the overall SOA margin during start-up >1.5 in order to compensate for this.

Step 1: Operating Conditions     Minimum Input Operating Voltage: VIN(MIN) 30 V              
 
Nominal Input Operating Voltage: VIN(NOM) 50 V  
  Maximum Input Operating Voltage: VIN(MAX) 52 V  
  Maximum Load Current: IOUT(MAX) 8 A  
  Maximum Output Load Capacitance: CLOAD 330 µF  
  Maximum Ambient Operating Temperature: TMAX 30 oC  
Steps 1 & 2: Operating Conditions, Current Limit, & Circuit Breaker      
     
                         
Step 2: Current Limit and Circuit Breaker   Current Limit Threshold Voltage 55 mV    
 
         
 
Maximum Recommended Value for Effective Sense Resistance 6.00 mW  
  Use External Resistor Divider to Reduce Effecitve RS No    
  Enter the Resistance for RS 5 mW  
  Recommended Value for RCL1 NA W    
  Recommended Value for RCL2 NA W    
  Enter value for RCL1 6 W    
Steps 1 & 2: Operating Conditions, Current Limit, & Circuit Breaker Enter value for RCL2 0.001 W    
Effective Sense Resistance (RS,EFF) 5.00 mW    
  Resulting Minimum Current Limit 9.7 A  
    Resulting Typical Current Limit 11.0 A  
    Resulting Maximum Current Limit 12.3 A  
  Maximum Power Dissipation in RS 0.8 W  
  Fault Response Latch Off    
      Circuit Breaker to Current Limit Raitio 1.9 x Current Limit                
Step 3: MOSFET Selection     Q1 FET Name CSD19536KTT  
 
           
 
Estimated MOSFET RQJA 30 oC/W  
  Number of MosFETs 1 #  
  MOSFET On resistance @ TJ,DC 3.5 mW  
  Maximum FET Junction Temperature 175 oC  
  100ms SOA Current (re-use 1ms data if unavailable) @ VIN(MAX) 100 A  
Step 3: MOSFET Selection 1ms SOA Current @ VIN(MAX) 16 A  
  10ms SOA Current @ VIN(MAX) 5 A  
  100ms  Current at @ VIN(MAX) (enter 'NA' if not available) 2.1 A  
  1s or DC SOA Current at @ VIN(MAX) (enter 'NA' if not available) 1.5 A  
Note: TI recommends choosing a FET with SOA current specified for 100ms and/or 1s or DC. If choosing a FET without these parameters, this calculator will estimate the values via extrapolation, which leaves an inherent associated risk. FET Power dissapation at full load (per FET) 0.2 W  
Maximum steady state FET Junction Temperature (TJ,DC) 36.7 oC  
Minimum Power Limit to Ensure Vsns > 5mV (PLIM,MIN) 52.0 W  
Target Power Limit 75.00 W  
Calculated RPWR 46.88 kW  
Actual RPWR 48 kW Note: Hover here to see the 3 values affecting this curve, consult a thermal expert if you are unsure!   
Actual PLIM 76.80 W  
Step 4: Startup     Load Turn-On Threshold 0 V
 
           
 
Startup Load Type Constant Current    
  Startup Load Value 0 A  
  Use External Soft-Start Control (dv/dt) No    
  Typical Start Time with Vinmax (Tstart) 5.87 ms  
  IFET - ILOAD margin (lowest for Vout range) 100%    
    Target Fault Timer: Tstart + Margin 8.80 ms  
    Target Timer capacitance 186.97 nF  
    Selected Timer capacitance  200 nF  
    Final Fault Timer(Tfault) 9.41 ms  
Step 4: Startup   Derated SOA / PLIM 3.22    
    Can a "hot" board be hotplugged No    
    Recommended slew Rate (max) 13.45 V/ms  
    Recommended slew Rate (min) 0.11 V/ms  
    dv/dt rate on Vout 2 V/ms  
    calculated SS capacitance 8.00 nF  
  actual SS capacitance 10 nF  
  actual typical dv/dt rate on Vout 1.60 V/ms  
  SOA margin during start-up 4.33    
  Target Fault Time 0.52 ms  
  Calculated Timer Capacitance  11.05 nF  
    Actual Timer Capacitance ( pick one smaller than CT,CALC 10 nF  
    Actual Fault Time (Tfault) 0.47 ms  
    SOA margin during "hot-short" or "start-into short" 3.22    
    Resulting Typical Insertion Delay Time 145 ms  
    Resulting Typical Restart Time 1881.29 ms  
Step 5: UVLO, OVLO & PGD Thresholds   Select Option A or Option B Option B                
 
Desired Upper UVLO Threshold 38 V  
  Desired Lower UVLO Threshold 35 V
 
  Desired Upper OVLO Threshold 65 V  
  Desired Lower OVLO Threshold 63 V  
  Recommended Resistance for:  R1 142.86 kW  
  R2 10.99 kW  
Step 5: UVLO, OVLO & PGD Thresholds R3 95.24 kW  
  R4 3.81 kW  
  Enter the Resistance for R1  150 kW  
  Enter the Resistance for R2  11.5 kW  
  Enter the Resistance for R3  95.3 kW  
  Enter the Resistance for R4  3.74 kW  
     
  Resulting Thresholds: Minimum Typical Maximum        
  Resulting Upper UVLO Threshold =  36.21 38.26 40.31 V      
  Resulting Lower UVLO Threshold =  34.41 35.11 35.81 V      
  Resulting Upper OVLO Threshold =  64.88 66.20 67.53 V      
  Resulting Lower OVLO Threshold =  62.02 64.20 66.38 V      
  Note: If any of the cells above are yellow, then these values are outside of the device's operating range. This will result in the device turning either on or off at its operating limits rather than at the user selected values in yellow.      
       
       
  Enter the Resistance for RPG 10 kW  
     
     
     
                     
Design Summary     RSNS = 5 mW              
  RCL1 = DNP W          
 
RCL2 = 0 W          
  RPWR = 48 kW Settings Units    
  CTIMER = 200.00 nF Current limit 11.0 A    
  R1 = 150 kW Power Limit 77 W    
  R2 = 11.5 kW Circuit Breaker Current 11.0 A    
  R3 = 95.3 kW Startup Time 5.87 ms    
  R4 = 3.74 kW Insertion Delay 145.5 ms    
  Cdv/dt = DNP nF Fault Timeout 9.41 ms    
  CIN 0.01 µF Restart Time During Fault 1881.294 ms    
  D1 B380-13-F   Upper UVLO Threshold 38.259 V    
  D2 DNP   Lower UVLO Threshold 35.109 V    
  Q1 PSMN4R8-100BSE   Upper OVLO Threshold 66.203 V    
  Q2 DNP   Lower OVLO Threshold 64.202 V    
  Z1 5.0SMDxx      
     
     
Notes: 1. Although not mandatory, CIN provides transient suppression at the VIN pin  
  2. A TVS clamp from VIN to GND is absolutely mandatory to clamp the voltage overshoot upon MOSFET turn-off, e.g. during circuit breaker  
  3. Componet tolerances not accounted for in Min/Max Calculations.  
                         

Start Up in to Short cases and inrush current limitation cases are happening as per the design requirements (Working).

We are facing the following issues during our testing,

1. During Hot start at the output, MOSFET is going bad.

Thanks and Best regards,

Adarsha V