UCD3138 FW LLC RESON_MODE _FIXED_DUTY _EN

The two threshold registers are for hysteresis. If you look at page 43 in the UCD3138 Technical Reference Manual, you will see a good illustration. However we don’t use the hysteresis in the LLC application because there is no discontinuity between the modes. Using hysteresis actually causes discontinuity. So we have both thresholds at the same value. 

While the two thresholds are different.

What is Auto Switch High Register?

I'm not sure what the question is - there is no auto switch high register there are auto switch high upper and lower registers.   They control when the DPWMAUTOMAX register is used.  They select when the DPWMAUTOMAX register is used,  When the previous DPWM value was below the lower register value, the DPWM value must rise above the higher register value before the control switches to DPWMAUTOMAX.  Once control switch to DPWMAUTOMAX, the DPWM value must go below the lower register value before control returns to the DPWMAUTOMID register.  

In Technical Reference Manual, page 68, Table 2-6. DPWM Control Register 0 (DPWMCTRL0) Register Field Descriptions (continued).

[12] RESON_MODE _FIXED_DUTY _EN Register

Configures how duty cycle is controlled in Resonance Mode
0 = Resonant mode duty cycle set by Filter duty (Default)
1 = Resonant mode duty cycle set by "Auto Switch High Register"

Then

Auto Switch High Register is auto switch high upper register while the DPWM value must increase from DPWMAUTOMID to DPWMAUTOMAX.

Auto Switch High Register is auto switch high lower register while the DPWM value must decrease from DPWMAUTOMAX to DPWMAUTOMID.

OK, now I understand why you are confused.  That's a bug in the TRM.  The correct explanation is here:

2.15.9 Resonant Mode Fixed Duty Enable The RESON_MODE_FIXED_DUTY_EN bit only controls the duty cycle width in the resonant modes. With the default (0) value, the duty cycle comes from the filter directly. This is for use above the lower resonant frequency, Fmin, and provides a duty cycle that fills half the period minus a fixed dead time. Setting this bit causes the pulse width to be derived from the Auto Switch High Upper Threshold Register. This bit is generally only set for LLC for the Sync FETs in the mode where the output frequency is below the lowest resonant frequency of the circuit. At this point any increases in pulse width are not beneficial, so they are stopped. There is also a waveform showing the modes in Section 2.10.1. This bit is duplicated in the AMS registers.