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BQ40Z80: AOLD\AOLDL activates immediately, ignores Delay setting

Daniel Librio
Intellectual 390 points
Part Number: BQ40Z80

Hi,

We'd like to better understand the AOLD protections setting if you're able to assist.
We find that on brief (<500ms) load current transients, out pack shuts down (DSG/CHG FET turns off), setting the AOLD and AOLDL flags.

Changing the Counter Dec Delay time appears to make no difference - it is currently set to 10s.

Is there a way to set a delay on this feature, so it isn't activated unintentionally by brief transients? 

I was able to adjust the Current threshold, and did see a corresponding increase in the transient the pack could withstand, as expected.  However it'd be good to also employ a time delay as our load is quite dynamic during operation.

Second question:  Are you able to suggest a source of supply for the BQ40Z80?  We're looking to buy 100-250 to support our next build (though ANY quantity would help!), and stock levels on your site and digikey are zero.  I'd prefer not to have to redesign our battery pack to use a different device at this stage of development, as you could well understand.

thank you,

regards,

Daniel

  • 0
    TI__Intellectual 2146 points

    Hi Daniel,

    You can try adjusting the OLD Threshold field. Bits 7 to 4 will set the delay on the flags, although the max delay of 31ms may not be enough for your application. If this is the case you can also try setting bits 3 to 0 to increase the threshold, which it seems like you've already done. In the worst case you can decrease the OLD Recovery field to minimize the amount of time FETs are turned off but of course this will increase the risks of overheating.

    We will get back to you on the second question.

  • 0
    TI__Intellectual 2025 points

    Hi Daniel,

    This device is very constrained in the current semiconductor environment. Octopart search results indicate the same as what you're seeing, no stock currently available at Digikey or Arrow. One action you could take is to click "notify me when available" in the order now section of the product page. If you're looking for a lower quantity for an initial prototype run, I might be able to provide you with some samples. Please connect with me offline if a lower quantity of samples may be of use to you. 

    Thanks,

    Rushi

  • 0 in reply to Albert Anwar
    Intellectual 390 points

    Hi Albert,
    Thank you, I'll attempt this tomorrow when I have access to a pack, and let you know how it goes.
    Just to clarify, is this the correct byte?  (currently highlighted in the image below?)  I was under the impression this byte only sets the current threshold?

    Incidentally I noticed that Appendix A of the TRM suggests values from 0x00 to 0x0F.  Ours is currently set to 0xFF in an attempt to set the current limit to the highest possible, short of setting the RSNS bit).  I believe the upper nibble was set 0xFx in the EVM, so I left it as is, and only changed the lower nibble to change the current limit.  Does the upper nibble matter?  Or is this upper nibble the time delay you refer to?

    Should I also attempt to set a latch limit above 0?  Is my understanding correct, that this may decrement each time there is an AOLD event exceeding the current and trip time duration, and that the pack output will not turn off until the counter reaches zero?

    Thanks again for your help with this!

  • +1 in reply to Daniel Librio
    TI__Intellectual 2146 points

    Hi Daniel,

    Yes, that is the correct byte. The upper nibble of that byte sets the delay, and the lower nibble sets the actual threshold. Although it looks like the byte is already configured for the highest possible threshold and longest delay, so you might need to set the RSNS bit (and adjust the ASCC, ASCD1, and ASCD2 thresholds appropriately).

    As for the latch, there's a latch counter that increments every time the threshold is exceeded, and can decrement if the current dips below the threshold for long enough. Setting the latch limit higher would not prevent shutting off the discharge FET (that occurs each time the threshold is exceeded), but it can prevent permanent fail (PF) of the device if that PF feature is enabled. 

    If all else fails, note that the value of the sense resistor affects the AOLD threshold value as well. A lower resistor would mean the threshold is higher and you should see less pack shutdowns.

  • 0 in reply to Rushi_Dalal
    Intellectual 390 points

    Sorry to raise this here, but I haven't heard from Rushi for some time, and we're quite nervous about obtaining some samples - if we cannot, we may have to find an alternative device for the next iteration of our design.  If someone can help out with this it'd be much appreciated!

  • +1 in reply to Daniel Librio
    TI__Intellectual 2025 points

    Replied via private message. Will keep you updated offline. 

    Thanks,

    Rushi