Hi team,
I got some questions from my customer below. Could you help me to answer the questions?
1. Could you tell me the VVBUS_UVLOZ specs(Min typ Max if you have)?
According to the datasheet, I2C interface will be available "when VBUS rises above VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ" but there are no specification on " VVBUS_UVLOZ" in the datasheet.
2. How long does it take for the POR to complete from UVLO unlock event?
According to the sentence below, host can access all register after POR but there are no description "how long does the host need to wait until register access will be available"
Here is the datasheet description about the POR behavior.
8.3.1 Power-On-Reset (POR)
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET driver are active. I 2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.
Regards,
Takashi Onawa
