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UCD9090-Q1: UCD9090QRGZRQ1 capabilities and HW design questions

Avner Cohen
Intellectual 460 points
Part Number: UCD9090-Q1
Other Parts Discussed in Thread: UCD9090A

Hi,

I am new to this type of health monitor and would like to know/verify some hardware things. ( without operating evaluation board.)

  • For the UCD9090QRGZRQ1 I did not understand how many GPIO function as output only, it can support.

23 is total. 2 can be input only. 10 can be used as rail sequence. What about the rest 11?  Can’t they be GPO digital outputs with logic behind them ? please refer to my attached schematics to see the intended use. In the schematics 12 use to control ON/OFF of dc-dc/LDO other 2 use also as outputs (digital) 3 optional.

 

  • Regarding the number of monitors: the UCD9090QRGZRQ1 have 11 monitors but the datasheet states 10 pg2. can’t I monitor voltages of 11 inputs? If it is only 10 on what pins the 10 located from MO1 to MON11? (I mean for voltage monitoring only, without the more sophisticated functions like margining.)
  • The Dc-Dc or LDO I use have power good signal (PG). Can I use the GPI as an input to check the status of the PG and combine the GPO controls of power sequencer, when both the 11 monitors and the PG participate in the logic ?
  • Can I use the reset pin to power cycle the card, using the FPGA ? in normal operation the RESET pin will be held pulled up by the resistor. When the FPGA (open drain output) will go low (as long as the FPGA is powered) the UCD will enter reset state and thus will shut down the power and rise it up again. Do you see that feasible?
  • I intend to use one of the GPO as reset out to processor and peripherals. (SEQ_POR_RESET in schematics)
    1. This pin should be low during power up and be delayed for minimum 2mS after all voltages stable. Can I make this reset +delay a combination of monitors & GPIs?   
    2. At power down, the Ti processor request that the reset will be prior to the decay of 3.3V and other voltages. In order to match this, I have to detect the falling of the 12V feeding the 3.3V DC-DC. That is why the 12V is monitored.(MON10) Thus, when the 12V will go down below predefined value, the Reset out pin will go low and stay low till the 3.3V decay.

Is that feasible? Can the logic behind the reset out pin can be programmed for different functions when power up and for power down ?

 

  • Can you please review my schematics and comment if something should be changed or taken care of ?

 

Thanks

  Avnerpower_sequencer.pdf

  • 0
    TI__Guru 65750 points

    Hello

    Please see my comments below.

    1. UCD9090A has 22 GPIOs. you can configure up to 10 ENABLE signal and up to 10 Logical GPO. The 10 Logical GPO can be used as ENABLE to control your power IC

    2. UCD9090A is a 10 rail device with 11 monitoring pin. the one extra pin can be configure as current or temperature as one of the 10 rail. even it is current or temperature monitoring, under the hood, it still monitor voltage.  you can configure the gain so that what you read is voltage instead of current or temperature. 

    3. you can have the PG signal connected and this can be as a condition or input to determine the output signal.

    4. we do not recommend use RESET pin to do the power cycle. PMBus has a dedicated PMBUS_CTRL pin which is a control signal to turn on or offer the rail. this signal can be used instead of RESET.

    5.1 yes, you can use the logic GPO to can take the GPI and rail statue as input to generate a output

    5.2. if you configure the logic GPO is a AND gate of the PG of all rail, when the 12V is below threshold, the logic GPO changes from HIGH to LOW since the AND gate does not hold any more. but do you want the signal back to high when 3V3 decays?

    Please refer our schematics guide line https://www.ti.com/lit/pdf/slvub50 

    Regards

    Yihe

  • 0 in reply to yihe
    Intellectual 460 points

    Hi Yihe,

    Thank you for your rapid answer.

    1. I did not understand the difference between the 10 PGOs that uses as  “Enable signal”  to 10 Logical GPO that “can be used as ENABLE to control power IC”

    Suppose I have 20 DC-DC each having control pin that power up/down according to logic levels. Let’s say threshold of 1.2V. Can all the 20 GPO have combination logic (of monitors and GPI) behind them to control the DC-DC?

     

    5.2 Regarding the question on section 5.2  “but do you want the signal back to high when 3V3 decays? Well no.  The plan is to detect the power down of the 12v prior to the 3.3V decay. perform reset to the CPU and make orderly power down of all voltages in the card. While the 3.3V will decay the UCD9090A will have no power since it is being fed from the 12V. it has time between the threshold set to the 12V to the time the DC-DC cease functioning so the GPO-reset will not go to high again. (For example decline of 12v from 11.5V  to 3.4V ).

    What do you think ?

      

    Thanks,

      Avner

  • +1 in reply to Avner Cohen
    TI__Guru 65750 points

    Hi 

    1. UCD9090A can configure to have a 10 dedicated GPO as ENABLE only. Those signal called ENABLE signal. For the ENABLE signal, they are associated with individual rail, you can set the proper turn on/off  dependencies(either other rail's status or GPI) so the ENABLE is fired based on those dependencies. 

    In addition to ENABLE, UCD9090A supports up to 10 LOGIC GPO, which can be a logic output based on the GPI, rail status. Customer can use these Logic GPO for many things, such as a SYSTEM_POWER_GOOD, FAULT_SIGNAL, RESET_SIGNAL or ENABEL signal. The GPIO of UCD is at 3.3V CMOS. You can refer the attached quick guide. 6038.UCD90xxx Quick Guide.pptx

    2. Yes, a AND gate of POWER_GOOD of all rails shall help to generate the RESET signal. you can also configure the fault response of the 12V, so when the 12V is below UV threshold, UCD can shutdown all the rails. Refer the fault response of the quick guide but you have to make sure that the the decay time of the 12V is larger than the time required to shutdown the whole system. 

    Regards

    Yihe