UCC24624: Roffset question

Hi, Hironori

I did not understand your question clearly.

The offset resistor Roffset is designed for programming turn off threshold VTHOFF for best efficiency performance, The external offset resistor value is recommended to be less than 212 Ω.

If Roffset is too big, the turn off threshold is high, then there could be negative current through SR MOSFET, Which lead to voltage stress from Drain to Source of SR MOSFET.

So there are two points to care about of SR:

1. Thermal of SR MOSFET and efficiency 

2. voltage stress from Drain to Source of SR MOSFET.

Yunsheng

Q1) Please let me know the mechanism of Fast gate off timing → slow off timing, but alternating when increasing load current.

If the gate off timing is always fast,Parasitic inductance causes a high drain-to-source voltage
I can see that the Vthgoff voltage goes above and off quickly.

You can see that you can adjust the resistance at the VSS terminal to raise Vthgoff.
I did not know the mechanism that alternates between fast to slow to slow off timing.

Q2)

When the drain current drops, the gate voltage is lowered to maintain the Vthreg voltage.
Is it correct to recognize that the Vthreg voltage does not change when adjusting the VSS pin, but only Vthgooff?

Q1: UCC24624 has proportional gate function, the gate voltage can be decreased when SR current is close to 0V then the turn off speed is fast.

In UCC24624, the proportional gate drive is disabled during the first half of the SR conduction time, based on the previous cycle's SR conduction time. Therefore, the gate drive voltage is only reduced during the SR current falling edge and this helps to maintain the low conduction loss. The gate drive voltage is forced to reduce if the SR voltage drop does not reach the proportional gate-drive threshold VTHPGD_LO within the 90% of the previous cycle on time. And the proportional gate drive now tries to regulate the VDS to –100 mV (VTHPGD_HI). This further ensures the fast turn-off speed for high di/dt conditions.

Q2: Yes, Vthreg is not changing with different Roffset

Yunsheng

Yunsheng, Would you please make more clear explain below ?  with some block diagram/ Hand writing waveform ? I could not understand it detail.

----- QUOTE ----

. The gate drive voltage is forced to reduce if the SR voltage drop does not reach the proportional gate-drive threshold VTHPGD_LO within the 90% of the previous cycle on time. And the proportional gate drive now tries to regulate the VDS to –100 mV (VTHPGD_HI). This further ensures the fast turn-off speed for high di/dt conditions.