This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS2492: About fig 13.

Guru 11255 points
Part Number: TPS2492

Hi team,

I'd like to know fig 13 in p.14.
Could you tell me the details of this operation?
I think it has three events.
I'd like to hear about each event.



Sincerely.
Kengo.

  • Hi Kengo,

    Thanks for reaching out.

    In this operation, the device is starting up in power limit mode.

    1st event: Current step = Plim/Vds where Vds = Vin-Vout = Vin as Vout is 0V at the instant of startup.

    2nd event: Current profile = Plim/Vds

    3rd event: current = current limit threshold = 50mV/Rsense

    Best Regards,

    Rakesh

  • Hi Rakesh,

    Thank you for your reply.
    I'd like to add a question for you.

    What kind of measures can be taken by attaching a capacitor to PROG?
    Ex: The output capacitor can be charged slowly. Is it right?



    Sincerely.
    Kengo.


  • Hi Kengo,

    Adding capacitor to PROG helps to slew the startup current (blue) instead of initial step as shown below. It does not provide significant advantage. So, we usually don't recommend adding capacitor to PROG

    Best Regards,

    Rakesh