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TPS7H3301-SP: Input Glitch

Kang Quan
Prodigy 100 points
Part Number: TPS7H3301-SP

We tie VLDOIN and VDDQSNS together, both inputs = 1.5V, when TPS7H3301-SP disable, there is no glitch on the inputs, but when TPS7H3301-SP enable, output = 0.75V, I find there is a glitch on inputs, it reaches to 1.2V for about 120uS. We have a RC filter between VTT_VO and VTTSNS, we know this makes the output 0.75V overshoot/undershoot nice. But the glitch still there on inputs. It looks like the old TPS7H3301EVM schematic suggests to isolate VLDOIN and VDDQSNS by adding another RC filter R=8K, C = 1uF between VLDOIN and VDDQSNS, but the new TPS7H3301EVM schematic doesn't give a value for the RC filter. I am just wondering if I follow the old TPS7H3301EVM schematic for the RC filter, can we get rid of the glitch on the inputs? if not, is there a way to remove the glitch on the inputs?

  • 0
    TI__Guru 62930 points

    Kang,

    I think you are indicating that your supply is sagging from the load when enabled?  Is that true?

    Can you provide a scope shot?  VLDOIN, VDDQSNS, VTT/Vo, Enable

    VDDQSNS should be a kelvin connection at the VDDQ supply at the DDR memory. 

    Is VDDQ and VLDOIN the same supply?  Can you provide schematic?

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 100 points

    Wade,

    Yes, VDDQ and VLDOIN is the same supply, I can provide schematic, and scope shots for VLDOIN, VDDQSNS and VTT/Vo, the question is how can I send them to you. I don't have a scope shot for Enable, and I don't think the enable matters now, as we already found a way to get rid of the glitch after I added 8.25K between pins and pads of VLDOIN. However, it causes the FPGA JTAG fails. I've tried to change 1K and 100 ohm, both have no glitch at 1.5V input, but FPGA JTAG fails. Until, I tried 1ohm, the glitch still there, but it is much smaller compare to no resistor, and FPGA JTAG works. Right now I am thinking maybe change to 2ohm, maybe the glitch will gone, and FPGA JTAG will work as well. But I just want to understand why we need to add a such small resistor in order to remove the glitch? maybe we have too big input capacitors?

  • 0 in reply to Kang Quan
    TI__Guru 62930 points

    Kang,

    You can post the schematic to this E2E.  If you are unable to post to public forum, I will send you an email so you can directly send to me.

    I am uncertain of your solution for improving the input glitch.  I am interpreting that you are adding a series resistance to the VLDOIN pad.   Putting a large resistance on the VLDOIN will definitely impact device operation.

    I am also uncertain of how this could be impacting the FPGA JTAG circuity.  Causing sag on the jtag supply?

    Having larger capacitance on VLDOIN should improve input glitching, as it will have more charge to supply the inrush current when it is enabled.   Possibly you have excessive capacitance on VTT/Vo?

    Please provide the scope plots and schematic.   To post to the E2E, you can click on the dropdown "Insert" and select "Image/Video/File".

    If you have a snapshot of the layout in this area it may be helpful as well.

    If you cannot post here, then reply back and I will email you.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 100 points

    I don't think I can send schematic in public, could you send me an email, thanks

  • 0 in reply to Kang Quan
    TI__Guru 62930 points

    I sent you an email.

    We can work this issue in email, then post resolution in post to close out.

    Thanks.

  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points

    This post was resolved offline.

    Primary resolution was to have device enabled during power up.  The upstream converters soft-start absorbed the inrush current requirements on VLDOIN and resulted in no glitch in VLDOIN.

    Kang,  please click "This Resolved My Issue" to close out this post.  Thanks.


    Regards,
    Wade