REF3312: REF3312

Hi Munir,

Is there any data regarding latchup on REF3312?

Yes, there is latchup data that is collected on this product.

Is the part CMOS?

That information is not revealed in the datasheet nor available.  Is there a reason for asking whether the part is designed in a CMOS or Bipolar process?

Ben

1) How can I get the test report

2) Bipolar do not latch with heavy ion while CMOS has potential for latchup

Are you seeking latch up at the pins or a space grade radiation tolerance?

electrical or for space

Ben and I belong to the commercial voltage references product line. All our product reliability testing involves latch up only at the pins - classicial semiconductor current injection type testing. If you seek space grade radiation tolerance I need to ask one of our sister divisions, hence I was trying to understand your application and reason for asking.

A lachup is function of the CMOS inverter characteristics.  I understand electrical latchup is current injection into the pins of a device. All inverters of a device are designed similarly.  So if it does not latch electrically, it is not expected to latch with heavy ion in space.

If you seek the commercial product reliability qualification information, it can be found on the product folders of the devices. For the REF3312, here is the link for your convenience: https://www.ti.com/quality-reliability-packaging-download/report?opn=REF3312AIDBZR

Hi Munir,

TI follows the JEDEC (JESD78D) standards when testing for latchup.  Whether the process being used to develop the IC is CMOS and/or Bipolar, TI applies the JEDEC standards for testing latchup in products that it releases.

Ben

My understanding is a bit different. Latch up at pins is different than latch up inside the device caused by ionized radiation (alpha particles in space). Electronics at the pins is often designed differently with guard rings and appropriate spacing to survive the standard JEDEC latch up testing. That can't necessarily be said about the internals of the device. I hope you won't make assumptions of the radiation tolerance of our devices based solely on the latch up performance at the pins. If you need to discuss this with someone in our space power team, I can assign this thread over to them.

Hi Munir,

Also, adding to what Ajay has mentioned, the devices themselves (usually CMOS devices) and the tubs associated with the NMOS or PMOS devices are usually tied down with P+ substrate taps to ensure the resistance between different tubs are low as possible to reduce possible latch up events.

Ben 

Hi Munir, 

Would like to point you to the list of space grade Shut References, please see page 21 in the appnote linked below

https://www.ti.com/lit/sg/slyt532h/slyt532h.pdf?ts=1627905398629&ref_url=https%253A%252F%252Fwww.google.com%252F 

Please share your application spec requirements to determine what is the best available solution (initial accuracy, LTD, noise, tempco). In the creative backlog we have a space grade series reference in plastic package. Please send me an email to antony.carvajales@ti.com if you would like to discuss more about the devices in the roadmap.

Thanks 

Antony 

Systems Manager

(Space power)