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BQ76952: what does alarm enable actually do?

Part Number: BQ76952

In the latest BQ76952 technical reference, the following are written about alarm enable:

"The 0x66 Alarm Enable() command can be read to see the present mask applied to the 0x64 Alarm Raw
Status() bits." on P60


"Mask for Alarm Status()." P93, p105

which one is correct?

  • also the following two sentences seem to contradict each other:

    " The bits in 0x64 Alarm Raw Status() can be selected to be latched"

    " The bits in 0x64 Alarm Raw Status() are not latched, so they may set only briefly."

    both on p60.

  • Hi Andre,

    I am not sure I understand where the confusion is. Maybe an example is helpful.

    In this example, let's set the Default Alarm Mask (RAM register 0x926D) to latch any protections, permanent fail conditions, or when any new measurements are ready. So let's set this register to a value of 0xF882. By setting this when we configure the registers (while in CONFIG_UPDATE mode) we are setting the default value of the 0x66 Alarm Enable register to latch all of these conditions.

    If we read from 0x66, it will show us which bits we have enabled, so it should read back 0xF882.

    Another thing we can do is to set the Alert Pin Config register to a value of 0x2A. This enables the Alert pin to drive a high logic level (assuming REG1 is enabled) to let the host know whenever the Alarm Status register has latched any of these events.

    Now, the Alarm Status register (0x64) can be polled by the host to see if any conditions are present. Alternatively, the ALERT pin can be used as an interrupt to the host. In the below example, the host polls the Alarm Status register. If it sees that new measurements are ready, it will go ahead and read the measurements and clear the FULLSCAN bit. If it sees that a protection has triggered, it will turn on an LED and clear the Alarm Status protection bits. It will later turn off the LED if the SafetyStatus register reports the protection has recovered.

    The Alarm Raw Status is not latched, so it might not be as useful for alerting the host since the bits will self-clear when the condition is no longer present. It may be useful for reading the raw information during debug.

      while (1)
      {
    
        //Reads Cell, Stack, Pack, LD Voltages, Pack Current and TS1/TS3 Temperatures in a loop
    
    		AlarmBits = AFE_ReadAlarmStatus();
    		if (AlarmBits & 0x80) {  // Check if FULLSCAN is complete. If set, new measurements are available
          		AFE_ReadAllVoltages();
          		Pack_Current = AFE_ReadCurrent();
          		Temperature[0] = AFE_ReadTemperature(TS1Temperature);
          		Temperature[1] = AFE_ReadTemperature(TS3Temperature);
    			DirectCommand(AlarmStatus, 0x0080, W);  // Clear FULLSCAN bit
    		}
    				
    		if (AlarmBits & 0xC000) {  // If Safety Status bits are showing in AlarmStatus register
    			AFE_ReadSafetyStatus();
    			if (ProtectionsTriggered & 1) {
    				HAL_GPIO_WritePin(GPIOA, LD2_Pin, GPIO_PIN_SET); }// Turn on green LED to indicate Protection has triggered
    				DirectCommand(AlarmStatus, 0xF800, W); // Clear the Safety Status Alarm bits
    			}
    		else
    		{
    			if (ProtectionsTriggered & 1) {
    				AFE_ReadSafetyStatus();
    				if (!(ProtectionsTriggered & 1)) {
    					HAL_GPIO_WritePin(GPIOA, LD2_Pin, GPIO_PIN_RESET); } 
    			} // Turn off the LED if Safety Status has cleared
    		}
    		delayUS(20000);  // repeat loop every 20 ms
      }

    Best regards,

    Matt

  • Hi Andre,

    (0x64) Alarm Raw Status () bits are transient.  If they are enabled in the mask (0x66) Alarm Enable() they will be latched into a status register at (0x62) Alarm Status().  The last few paragraphs of section 6.6 on page 60 describe that.

    Page 93 has the table of commands where they are listed without the commentary but the access is described.

    Page 105 section 12.2.19 Alarm Enable Register is the bit definition for the mask or enable bits.  Table 12-19 for the bits though seems to be a copy of the bit definitions.  When an Alarm Enable register bit is set it allows the corresponding transient condition in the Alarm Raw Status to be captured or latched in the Alarm Status. 

    Thanks for pointing this out.  I will flag this for update in a future version.

  • thanks guys. To clarify, I was confused by the wordings. I think I get it now, the Alarm Enable enables/disables for both Alarm Status and Alarm Raw Status.