Hi,
I'm currently using TPS54231 in my circuit design & encountered a situation whereby I'll need to use 47nF Css to solve some inrush current issue on my board. I know that with the use of 47nF, I've prolong the Tss timing requirements exceeding the recommended 1~10ms range as shown in datasheet. Hence I would like to know what are the possible consequences I might run into with this setup & any design recommendations I can take to optimize my design?
Hello,
As stated in datasheet, to ensure good startup behavior, the slow-start time should be set between 1 ms to 10 ms. Hence the value of the capacitor should not exceed 27nF.
"I would like to know what are the possible consequences I might run into with this setup", please find them below.
Methods to Reduce Inrush Current
Inrush current can be reduced by increasing the voltage rise time on the load capacitance and slowing down the rate at which the capacitors charge. Three different solutions to reduce inrush current are shown below: voltage regulators, discrete components, and integrated load switches.
Please click on the link below for an app note on how to Manage Inrush Current
www.ti.com/.../slva670a.pdf
Best,
Jose
