LP87565-Q1: LP87565-8A-8A PMIC destroyed

Kevin Huang67

Part Number: LP87565-Q1

Hi sir,

When I used LP87565-Q1 for power distribution to 8 power domains(every channel 8A for 4 power domains, every power domain 1.5A and has sense trace to FB), the software engineer run the voltage adjusting about 2 hours to let the LP87565-Q1 input 5V short to GND.

What's the possible reasons to let LP87565-Q1 input 5V short to GND?

The first 4 power domains have total 800uF cap. near main chip and every power domain has sense trace to FB_B0.

The second 4 power domains have total 400uF cap. near main chip and every power domain has sense trace to FB_B2.

if the de-coupling cap. are too much to let sense abnormal ?

How can I avoid the fail situation ?

over 4 years ago

0 Tomi Koskela over 4 years ago

TI__Genius 11020 points

Hello,

For that high capacitance on the buck outputs there is limitation on how fast slew rates can be used. Please see below for table from datasheet:

- What is the slew rate setting you are using with this system?

- Do you have snubbers placed on each SW node? This is requirement for systems with 5V input voltage.

Thanks.

Regards,

Tomi Koskela

0 Kevin Huang67 over 4 years ago in reply to Tomi Koskela

Intellectual 410 points

Hi Tomi,

1. I think that our software engineer use the default slew rate setting for output voltage.

2. What's the snubbers placed on each SW node for 5V input ? Please help to explain it. Thanks!

0 Tomi Koskela over 4 years ago in reply to Kevin Huang67

TI__Genius 11020 points

Hello Kevin,

1. What is the full orderable part number? We have several LP87565 spins which each have different settings.

2. Datasheet section 9.2.1.4 tells more about the snubbers.

Thanks.

Regards,

Tomi Koskela

0 Kevin Huang67 over 4 years ago in reply to Tomi Koskela

Intellectual 410 points

Hi Tomi,

1. LP875650RNFRQ1

2. I had added the snubbers on each SW node.

0 Tomi Koskela over 4 years ago in reply to Kevin Huang67

TI__Genius 11020 points

Hello Kevin,

1. You can see the default setup for this orderable in https://www.ti.com/lit/ug/snvu641/snvu641.pdf . It is set to 3.8mV/us slew rate. So for 800uF total capacitance slower slew rate setting should be used. 1.9mV/us slew rate setting allows using 500uF/phase, so that is 1000uF for dual phase. Too fast slew rate setting compared to the output capacitance can have caused damage to the device.

2. That is good then.

Thanks.

Regards,

Tomi Koskela

Power management

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LP87565-Q1: LP87565-8A-8A PMIC destroyed