BQ769142: Short circuit and damaged BMS

Hi Hamzeh,

Willy (WM5295) is out of office this week and I know he was helping you with the short circuit test issue on this other thread: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1026628/bq769142-bq769142-short-circuit-test

He will be back on Monday, so I'm going to assign this question to him as well since he has the most experience running short circuit testing on this device. I know a few things that may be helpful best practices, but I don't know if any of these apply to your hardware:

• The FET gate resistance in series with your CHG and DSG pins should not be too small. Switching the FETs too fast will cause large transients, so we use a larger resistor on the EVM to prevent damage to the components and FETs. Hopefully the voltage rating on your FETs is high enough - we use 150 V rated FETs on the EVM.
• A larger RC time constant can help reduce amplitude of transients - we use 20 Ohms with 0.22 uF on the cell inputs for the EVM.
• Hopefully you have enough FETs in parallel to handle the peak currents for your application. There is an app note on using multiple FETs with the BQ76952 that is very helpful for selecting gate resistances, the charge pump capacitor size, and other useful circuits for optimal FET switching.

Best regards,

Matt

Hi Matt,
I've updated this to better explain my setup and problem. I hope Willy can have a comment on this. BTW, thanks for the sluaa09 (application notes about multiple FET). It has a section about short-circuit.
system setup:
 - battery: 48V 13s-6p
 - CP1: 220nF (I learnt I can increase up to 2uF for faster switching), CHG/DSG resistor: 5.1K (like reference schematic).
 - FETs: two directly parallelized FETs (150V, Rds~16mohm, 60A constant) for each case. I can't have more. I learnt I should put small separate gate resistor for them. I saw 15A discharge current with 50-60 degree heating.
 - FET protections: source-gate zener, load under voltage .... (same as reference).
 - SCD setting: 80A, delay 15us
 - digital ground is on load side of current sense (I was told here that it is better to move it to BAT- side...). due to this I always see a around 10-20mA of discharge, even if load is open.
Problem:
I suffer from bms board damage after having a quick short-circuit contact on load side with large spark which burned my finger. I repeated this test two times. After test FETs are damaged. They are shorted, in a way that charge-pump voltage is visible on load side. Replacing the FETs and charge pamp capacitor and some other things solved the problem. in sluaa09, it is said that source-gate zener protects the FET in short-circuit, then I guess my problem is that CHG FET does not turn-on quickly in response to short-circuit and body diode is burned.
If the problem is this, I can increase FETs turn-on speed like sluaa09, but still there is no guarantee. maybe turning "SLEEPCHG" in FET options also can help in cost of more power usage. What is a definite solution? is per-discharge for this?
- when I open "SLEEPCHG", I see CHG is also ON in sleep mode, then a sudden in-rush, like short-circuit will not burn the CHG diode. this can help

- but when I activate pre-discharge, in relax(sleep) mode, DSG is always ON (because pre-discharge-stop-delta is already met. open load has almost same voltage as Bat). If there is a way that PDSG to be ON in relax mode always, then a sudden in-rash would be under control.

Thanks

Hi Hamzeth,

I'm not sure if I understand the present situation.  With an unloaded pack and a high impedance measurement tool it is common to measure nearly the charge pump voltage on the PACK+ terminal when the charge FET is off.  The charge pump voltage is applied to DSG, the RGS resistor (10M typically) pulls up the PACK+ terminal and turns off the discharge FET until some load on PACK+ pulls down the source of the discharge FETs to turn them on. A 10M impedance meter measuring PACK+/- is sufficient to turn on the FET.  It seems you have had real damage though and have solved it with FET replacement.   Shorted terminals on a discharge FET with the charge FET off (part is asleep) would put the charge pump voltage on the PACK+ through the DSG pin and shorted FET.  A charge FET with gate to drain short leaving the source open would also allow this, I don't know how common that type failure may be.

The Zener across the charge FET gate-source (D2 in the circuit below from SLUAA09) is important to prevent damage to the charge FET during SCD.  BAT is held up by the filter capacitor and its discharge is blocked by D1.  If BAT is 48V and the Q2 gate is 48V (CHG and FET off) or Q2 gate is 59V (CHG and FET on) and the pack is shorted, PACK+ and the FET source and drain will go to near 0V, the FET VGS would be about 40V, exceeding the 20V abs max typical for power FETs and likely damaging the power FETs.  There are FETs with higher VGS limits, but they are unusual.  Check your part's specification, but typically the Zener diode is required.  D5 is needed similarly for the discharge FET Q5.

With series FETs the charge FET is typically the same as the discharge FET since it must handle the pack current.  Looking at the safe operating area curve of a power FET the dissipation of the FET with about 1V VDS (about the magnitude of the body diode voltage) is typically the maximum current capability of the FET perhaps all the way to DC, so the power into the FET from a brief SCD event is not expected to be damaging.  Check with your FET vendor for any specific interpretation of the specifications as they apply to that part and this situation.  If the charge FETs were made smaller due to lower charge current then those FETs would be more appropriate for a separate charge path.  If using a separate charge path be sure the paths are protected for the events needed in your situation.  Sometimes the discharge path needs charge protection and separating the paths may not be appropriate.

If the body diode drop is causing damage to the charge FETs keeping the charge FET on during sleep may be an appropriate setting as you note.

Pre-discharge operates only for a time or voltage when the DSG is turned on, so it will not be always on.  When it is time to turn on DSG the predischarge path will come on first, and when the time or voltage of LD is met the DSG will come on.   So if the battery is on and plugged into a large capacitance there may be a short circuit due to the inrush to the capacitance.  When the BQ769142 recovers it will use the pre-discharge circuit and sequence which should avoid the inrush, but that is after the initial event.  If you have a circuit which detects connection to the system then turns on the battery output the pre-discharge would activate to avoid the inrush.  

Thanks Willy,

The first point is, I almost always see CHG=OFF, DSG=ON in open load (BMS in sleep). Then I see BAT+  minus ~1V drop (CHG body diode, DSH resistance) on Load side.  As I understand from your comment, this is not normal.If I can see DSH=OFF in sleep mode, my problem is solved, as short-circuit will not cause a sudden damage (even per-discharge can prevent it). When I have open load, I never see current=0mA on CC2, but  I see something around -10-20mA. I have digital ground connected on load- side (not BAT-) side and then BMS and MCU current is counted in current consumption. is it the reason I always see DSG=ON in relax mode?

Dear Willy,
thanks for your response and sorry for too long questions. Let summarize it:

- For my application, the default sleep mode setup: CHG=OFF, DSG=ON can be dangerous, since an strong in-rush, short-circuit, etc., damages CHG body diode. Then to be safer, I use SLEEPCHG to keep CHG ON too, in sleep. This is not bad.

- even for better solution, if I want to use pre-discharge for smoother load transition, I need to decide to turn-on the DSG(and then PDSG) just after connecting the load, not earlier otherwise can't see pre-discharge effect. I wonder if I can handle this with MCU. I can keep ALL_FETS_OFF and then release them after detect a load, but how can I detect a load when there will be no current as all FETs are off. I can keep pre-discharge FET somehow on (by continuously do ALL_FETS_OFF and ALL_FETS_ON in a loop) but even with this, still detecting a load is difficult, because current of pre-discharge mode is already very low and indistinguishable ( I really wonder where pre-discharge is effective in practice).

Then it seems there is a trade-off. I can't handle everything together.