LMR14020-Q1：cispr25 class5

Hello,

Can you send a picture of your schematic and board layout? 

Also what frequency range are you failing?

I would follow the layout Guidelines as well as the layout example provided in section 10.1, 10.2 of the datasheet. I've attached an app note that offers a good starting place for input EMI filter design. 

simple success with conducted emi from dcdc converters.pdf

Regards,

Harrison Overturf

Hello
Is it possible to keep the information private?

The board has two layers and only the power supply IC part is extracted.
Thank you for your consideration of the content.

Hello,

I've deleted the images you sent previously to keep the information private. 

I have a few comments regarding your schematic and layout:

• Include a high frequency input capacitor (100nF) placed as close to the Ic as possible. Move C11 and C12 to the right and insert this capacitor between C12 and R13. 
• Try to shorten the total path between SW and Cboot (C9) and BOOT pin. 
• The feedback network is too close to the SW node. It is better to place the feedback components close to the FB pin and instead have a trace routed from Vout to the FB network. 
• Rotate the inductor by 90 degrees counter clockwise in order to shorten the path from the GND of the output capacitor to the PAD of the IC. This will reduce the size of the output loop. 

See Section 10.2 of the datasheet for a layout example. 

Regards,

Harrison Overturf 

I thought about the board layout, so please consider it.
・ Is there any problem with the two layers of the board? The prototype board will have two layers, and the mass-produced board will have four layers.
-Should the distance to the connector be the shortest with vin and vout?
・ Is the 100nF capacitor a bypass ceramic capacitor?
Please delete the drawing when you see it.
I look forward to working with you.

Hello,

I accidentally deleted your last response as well as the images, but luckily I saved the response as well. 

It will be easier to pass CISPER25 class 5 with a 4 layer board because you can use the MidLayer 1 as a GND layer. This will help dissipate heat as well as act as a shield for signal traces placed on MidLayer 2. This GND plane can also reduce ground loops as well as absorb EMI radiated from the inductor. 

Yes the 100nF input capacitor is a ceramic. The new layout and schematic look good as well.

One other point I need to stress is that you will need an input EMI filter in order to have the best chance of passing the CISPER25 Class 5 standard. Please refer to the pdf I sent you originally to get started with the filter design. 

Lowering the switching frequency will generally make it easier to pass, but you'll still need to follow these guidelines.

Regards,

Harrison Overturf 

Hello.
It is a 4 layer board. Is it correct to imagine that midlayer2 is sandwiched between midlayer1 and bottom layer? Please let me know if there is anything I should be aware of in terms of spreading via and GND when using 4 layers.

Also, can you confirm whether the circuit constants are optimal for 360kHz?
After checking the diagram, please delete it.
Thank you very much for your help.

Hello,

Yes midlayer2 will be sandwiched between midlayer1 and the bottom layer. The vias will help by:

1. Ensuring electrical connectivity between grounds on different layers, thus ensuring a stable ground.

2. Helping dissipate heat to different ground planes. 

Since you are creating a 4 layer board, check out the EVM user guide for an example of how to layout the board. The midlayer1 is entirely Ground pour, midlayer 2 is the signal layer with signal traces as well as primarily ground.

The circuit component values appear to be correct for your use case. When you have completed your layout send pictures to me and I will review. 

Regards,

Harrison Overturf 

Thank you for your help.
thank you for your answer. I'm sorry for the gap.
CISPR25 class 5 fails at 0.72MHz and 27MHZ against the switching frequency of 0.36MHZ in the previous circuit. What are the most effective filter circuits and improvements? Thank you for your consideration.

Hello,

Are these the results with the input filter included? If so can you share the new board layout with the filter included?

Regards,

Harrison Overturf   

I put the filter circuit on the old layout prototype board I showed you last time. I have not been able to remove the noise yet. The layout of the board will be discussed in the future. The new board layout is not ready yet, but please check it out when it is.

Hello

Sorry for the confusion. This is the result of CISPR25 CLASS5 testing by hand mounting the components marked with red circles and red letters on the old layout prototype board. Is it difficult to comply with CLASS5 or CLASS3,4 without changing the board layout? Thank you for your continued support.

thank you

Hello

The coil is a low DC resistance, closed circuit structure.
Is it correct to select a low ESR aluminum electrolytic capacitor?
Thank you for your consideration.

Hello,

In terms of the components you have just sent over:

• The Cf capacitor should be a smaller ceramic capacitor, not an electrolytic cap
• The filter inductor Lf that you are showing is 47uH which seems too large for this application. The previous app note AN-2162 recommends a maximum value of 10uH for this inductor.
• The Cd capacitor that is shown is acceptable.
• The boot resistor is shown as 75Ohm, which is too large and may result in the high side FET not being able to turn on properly. This resistor should be decreased to be less than 10Ohms. 

You previously sent over a schematic with the following component values:

Cf = 10uF, Lf =3.9uH, Cd = 100uF.

Have you tried running the EMI test with these component values?

Regards,

Harrison Overturf 

Hello.
Thanks for the advice.

With 2 layer board and aerial wiring
Cf = 10uF, Lf =3.9uH, Cd = 100uF
I made a prototype with 10Ω boot resistor, 10Ω snubber circuit + 330pF.
(Following the circuit diagram of 5 days ago)
This is the power supply line, and there is 260 to 300mV of switching noise on it.
I'm going to try CISPR25 test, is it ok?
I'm worried about the 2nd harmonic.
Please delete the filter circuit diagram from 5 days ago.

I am troubled by the fact that the actual waveform I see on the oscilloscope and the CISPR25 results are different. Is it possible to know the judgment criteria without CISPR25 testing equipment (anechoic chamber)?

thank you.

In the oscilloscope waveform, I am looking at the entrance of the filter circuit (Cf = 10uF, Lf =3.9uH, Cd = 100uF) and the power line in AC mode. I would appreciate your consideration and answer.

Hello,

I would expect to see some switching noise on the input due to the discontinuous switching currents at the input to the buck, but the magnitudes you are measuring seem larger than I would expect. This could be due to probe set up, please follow the the low inductance probe technique shown in Section 3 of https://www.ti.com/lit/an/slva494a/slva494a.pdf and measure directly across the Cf capacitor. 

I'm not sure what you mean when you say: 

masahiro fujiwara said:

Is it possible to know the judgment criteria without CISPR25 testing equipment (anechoic chamber)?

Using a dedicated CISPER25 test set up is the best way to evaluate whether your design will pass CISPER25 emissions standards. 

Regards,

Harrison Overturf