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TPS650864: Sequencing of DDR with TPS6508640

Epzkon
Prodigy 60 points
Part Number: TPS650864

Hi,

I am currently looking on the TPS6508640 for powering a ZU15EG.

In the block diagram at page 24 in  "TPS650864 Configurable Multirail PMU for Xilinx® MPSoCs and FPGAs"

i see that external DDR memory can be powered using BUCK6, VTT LDO and LDOA1.

In the sequencing chart on page 25 it looks like the LDOA1 which powers VPP starts ramping at BUCK6 PG (BUCK6 powers VDD/VDDQ).

However in the datasheet of my DDR memory the sequencing is, VPP has to be ramped prior to VDD/VDDQ and VPP > VDD/VDDQ through the whole ramping period.

I havent been able to understand if it is possible to configure the sequencing of the TPS6508640 in such a way that it satiesfies the DDR sequencing?

With the "standard" sequencing configuration it looks like VDD/VDDQ will be ramped prior to VPP.

  • +1
    TI__Genius 13216 points

    Hi,

    You are correct that with standard sequencing, VDDQ will ramp prior to VPP. Some solutions to this could be leaving CTL1 as 0 and sequencing enabling these resources in the desired sequence over I2C. Additionally, you could use a previous powergood as an enable for an external device to supply VPP before VDDQ.

    Thanks,

    Daniel W

  • 0 in reply to Daniel W
    Prodigy 60 points

    Hi,

    I understand. I was not sure if LDOA1 was configurable using I2C. It is correct that i can use the SWB2_LDOA1_EN bit in RAIL_EN2/GPOCTRL register is for this purpose?

    Thank you for the reply.

    Epzkon