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TPS53681: TPS53681 PWM/CSP layout routing constraint requirements

user6304695
Prodigy 120 points
Part Number: TPS53681

Hi

     I want to know the driving ability of PWM and CSP(=CSD95490Q5 IOUT pin) pin,

1、how far the pcb layout  routing？10inch？

2、Is there skew constraint between multiphase PWM？

shaocong

thanks

  • 0
    TI__Expert 3525 points

    Hi Shaocong,

    We don't have formal guidance on trace length as the parasitic capacitance may not affected by other layout factors. Higher load capacitance may more cause issue but may slow down the slew rate of PWM signals.

    For CSP pin, it's driven by the IOUT pin from power stage. The IOUT/REFIN from power stage is voltage mode output which generates typical 5mV/A signal to sense/monitor the inductor current. 

    We normally suggest to keep PWM traces away from switching node, high noise/high voltage(12Vin vias, copper and traces), high current by using spacing at least 40mil. and also keep 30mils gap between PWM traces with min trace width >=7mils.

    For power stages in multiphase applications, the phase pitch between adjacent phases should be maximized whenever possible to prevent any cross-coupling noise between devices(9mm or larger is preferred).