customer having issue with TPS7A26 power/reset circuit performance.
datasheet indicates PG floats to the pull up voltage when Vout exceeds 93% of the targeted Vout voltage, and PG uses open drain to pull low when Vout drops below 90% of the targeted Vout voltage. Is this correct?
Hi Carl,
See the image (taken from Digikey) below. The PG pin is driven to a high impedance (i.e. the FET is turned off) when the output is above 93% of its target. In this case very little current (only drain-source leakage current) flows so very little voltage is dropped across R and the PG pin sees the VCC voltage. When the output then falls to less than 90% of its target, the FET is turned on and current flows, dropping most of the voltage from VCC across R such that the PG pin voltage will be near 0V (usually ~0.4V or less).
Can you share more details for your customer's application?
Regards,
Nick
