Power protection using wide-bandgap devices

Hi,

This is Divyanshu, Application support for power switches. A customer is using a solar array output of 100V to charge a 15V battery at the output through a DC-DC buck converter. But our power protection devices are not rated for such high input voltages. I was wondering if you have come across such applications before, where wide-bandgap devices are used for power path protection in very high voltage systems?

Here is the link to the e2e query for your reference: e2e.ti.com/.../1037169

Thanks and best regards,

Divyanshu

  • You are using the wrong type of solution. The reverse flow change is relatively slow so you can do it using more basic components and reach your target voltage. 



    This is simulated and implemented but the components are 40v rated. Swap the PNP's and PFET for something higher rated. Also note the PNP's should be matched so use a package like MMDT5551 (160v rated). 

  • Hi Andrew,

    Thanks a lot for sharing, seems like a wonderful scheme to obtain reverse current protection. Phillip, do you see any concerns from your side?

    Can you please provide the simulation/implementation results for this approach. We can then make changes to the simulation to accommodate higher voltage levels. Thanks a lot for your help!

  • It's widely used. The difference is it's using a pull-down on the gate which is not as fast as a driver IC like the chip you've looked at (although 47k is still reasonably quick). In your case solar is slow so you won't care.

  • Hi Andrew,

    I appreciate your suggestion. This looks like it would work, but I am looking to avoid a PFET solution for the following reasons:

    1. Depending on how the solar panels are configured by the user, the maximum current can be up to 15A. I'd like to avoid generating so much heat in the much higher rds of a PFET. I quickly browsed what is available on Digikey, and in the same price range the rds of NFETs is between 10 to 20 times less than comparable PFETs. I understand I have to sacrifice some heat and power to implement this protection, but I would like to keep it minimal as there are several other heat sources downstream.

    2. There are just so many more NFET options in this current range in general, which will make specing alternatives easier if needed.

    I realize this could be implemented on the low side with NFETs, but due to one of the failure scenarios, protection is required on the high side.

    It looks like a circuit similar to that described in SLUA486 would work, but I'd prefer a simpler solution if there is one.

    Thanks,

    Phillip

  • If you don't know it, MOS with lower RDS (and higher gate capacitance) are paralleled and there's nothing stopping you doing the same. 

    With NMOS you need a gate voltage 5-15v above the output so say 20v. Use the same circuit but wire the PMOS gate to a inverting driver and a small LDO from the solar into a boost to gain the stable 20v drive. Of course the additional cost, complexity and loss through making the driving voltage and driver will likely be more than the loss of paralleling several PMOS.

  • I've seen the floating tricks before to move GND, it gives you a higher ceiling but does so by moving the floor. For your application you have to pick the best compromise and while a PMOS of a low rds costs more you've saved it by using a $0.03 chip vs whatever the TI chip costs. That's not to discredit the TI chip which undoubtedly being a driver circuit is much faster then a pull-down resistor but in your case the speed isn't needed. For solar the circuit above is widely used. I reckon solar is so slow you could possibly link the PMOS gate above into a MCU for hysteresis and drive a relay.

  • Thanks for your feedback, Andrew! Unless anyone has further comments, I'm going to consider this issue resolved.

    Best regards,

    Don