ACGUY,
I believe you are referring to the UVLO on/off voltage threshold levels and they are given on page 3, of the UCC1891 data sheet as below. 13.2V is the maximum turn-on voltage, 8.4V is the maximum turn-off voltage:
Regards,
Steve M
ACGUY,
You are referring to the UCC2891 internal JFET which allows start-up directly from VIN<110V. VIN is internally shorted to VDD through the JFET and ~15nA of current is sourced into the VDD capacitor. The 15mA current charges the VDD capacitor until VDD>13V, which results in the JFET being open which disconnects VIN from VDD. During this time the UCC2891 is switching but the VDD capacitor is also discharging. Bias voltage must be provided to the VDD pin before the VDD capacitor discharges down to 8.4V. This essentially establishes a race condition that must be satisfied by i=C*(dV/dt), where i=15mA, dV=13V-8.4V=4.6V, C=chosen VDD capacitor value, dt=time required for the VDD bias to reach >8.4V.
For UCC2891 reference design examples you can view the TI Reference Design Library here. UCC2897A is another active clamp controller that has internal JFET start-up.
Regards,
Steve M
