TPS6594-Q1: VIO_IN 1.8V from LDO output of TPS6594

There are a few items to consider in determining if SoC PDN-0B/0C can transition to using 1.8V for PMIC's VIO_IN.

1. Is there an "always ON" 1.8V supply that is energized independently & remains on during all SoC operations?

If Yes, then PMIC VIO_IN could be connected to this "always ON" 1.8V supply assuming all control signals sourced from PMIC GPIO ref to VIO_IN and connected to other system discrete components (Load Switches, LDOs, Bucks) can use 1.8V logic signals. The 1.8V needs to be "always ON" since the load switches supplying 3.3V to SoC VIO supplies are enable at T0 = 0ms of the SoC power up seq.

If NO and you tried to supply the 1.8V from a PMIC Vo, then the control signal to enable the 3.3V load switch would not be asserted at beginning of power up seq (T0=0ms) since the PMIC's 1.8V Vo do not get energized until (T1 ~2ms) after all 3.3V supplies are enabled. This would delay 3.3V turn-on by ~2ms and result in 3.3V & 1.8V supplies being at best case energized concurrently & probably more likely the 1.8V would lead 3.3V due to load switch turn on delay & slower ramp time. This can lead to current bleeds inside the SoC that will have negative impact on PoH reliability.

2. Does SoC need a 3.3V supply input to support any signaling (i.e. CAN, SD Card, USB2.0)?

If YES, then VIO_IN is typically connected to the VCCA_3V3 (protected side of the in-line safety FET) in order to properly enable PMIC GPIO9 (ref to VIO_IN) to drive to a logic high at time T0 of power up seq. You should not use 1.8V PMIC Vo as described above.

If NO, then all current SoC 3.3V supply inputs would need to be moved to a 1.8V power rail. The additional loads being added to 1.8V rails will need to be checked to verify sufficient positive current margin is maintained. Assuming no issue with overloading any 1.8V power rails, then the PMIC VIO_IN could be supplied from a PMIC 1.8V Vo. The correct 1.8V Vo will depend on whether your system is implementing any low power modes (MCU Only or DDR Retention). You will need to ensure all PMIC GPIOx with output buffers reference to VIO_IN are not needed during a low power mode that might disable the 1.8V supply to VIO_IN.