This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLC59283: Daisy chaining the TLC59283 led driver

Part Number: TLC59283

So, first off: I have successfully daisy chained the 8bit led drivers from the TLC591x series.

This worked just fine, with 10 of them chained. After writing 9 more bytes, the latch register of the last matches what the first register used to be.

I have now switched to a very similar device, albeit 16 bit: TLC59283.

Everything works fine, except the chaining. I am not getting the expected bits on SOUT/SIN.

Even after mimicking the samplecode shared on this forum, with same signalling order, and same timing, the chained device sees unexpected data.

Is there a fundamental difference between TLC591x and TLC59283 on how the last bit is shifted out of the register into SOUT?

I expect that if I write a 16 bit pattern twice, then both devices will show the same latch output, with the chained device getting fed the contents of the first device.

To be clear: I have wired the devices as shown in the datasheet: SOUT of first device connected to SIN of second.

LAT, CLK are shared between them.

  • Hi Abraham,

    The interface protocol of TLC5928x is similar with TLC591x. The input bits are shifted to SDO by rising edge of CLK. I think there may have some transmission delay from your controller to TLC device, making the interface timing nonstandard. Could you help to capture the waveform of SIN/CLK/LAT/SOUT for both device, on the IC pins, to check the timing?

  • Thank you, Hardy.

    It is good to know they should be the same. I will try to capture the signals.

    It does puzzle me that it shifts at rising edge, because, the data is shifted into the register with rising sclk as well!

    Page 15 of datasheet: "The data at the SIN pin are shifted into the 16-bit register LSB at the rising edge of the SCLK pin; SOUT data change at the SCLK rising edge."

    So when the data is shifted in, the SOUT is still in the process of getting set. How could this work?

    Should there not be a stable SOUT status before you could shift that into SIN of the next IC in the cascade?

  • I have determined one of my chips has a defect.

    I have replaced it with a new IC, and now I see the daisy-chain work as expected.

    I expect I either killed the chip with my heat-gun when soldering it (I use the gun at 300 degrees C, is that appropriate for this part?) or I killed it with ESD. Is the TLC59283 exceptionally fragile, maybe?

    Anyways, it works now.