TPS6594-Q1: PDN-0C GPIO11 of 1111 in TO_MCU/PWR_SOC_ERROR

Hi Oguri,

  Would you please explain more details about your question? Maybe with some pictures? I don't understand the question.

Thanks!

Phil

Hi Phil,

Thank you for the feedback. My question is why GPIO11 is not involved in PWR_SOC_ERROR while it is in TO_MCU and even it looks like a part of SOC domain.

There is another similar question:

Why LDO1 of 1111 is involved in PWR_SOC_ERROR and TO_MCU, even though it is configured as "No group assigned" in Table 5-7? It looks as if a part of SOC rail group. What is the difference from other SOC rails?

Thank you again.

Regards,

Oguri

Hi Oguri,

 There is no read-back on all GPIO pins even they look like a part of SOC domain, so PMIC does not take any action for GPIO level incorrect.

 LDO1 of 1111 is involved in PWR_SOC_ERROR and TO_MCU by PFSM, not by configured as "No group assigned". It looks like the LDO1 needs some delay and other SOC rails don't have delay. I'll check with system designer to confirm and update you later. 

Thanks!

Phil

Hi Phil,

So, you mean because PWR_SOC_ERROR is triggered when one or some of the rails of SOC rail group has incorrect level? (I am not sure when PWR_SOC_ERROR is triggered.)

I thought PWR_SOC_ERROR and TO_MCU are controlled by the grouping shown in the "Table 5-7. FSM NVM Settings". If no, what purpose the groups in the Table 5-7?

Thanks!

Regards,

Oguri

Hi Oguri,

  Yes, PWR_SOC_ERROR is triggered when one or some of the rails of SOC rail group has incorrect level but not GPIO; and PWR_SOC_ERROR and TO_MCU are controlled by the grouping shown in the "Table 5-7. FSM NVM Settings" except GPIOs. 

Thanks!

Phil

Hi Phil,

Thank you for the update.

I still need your update on LDO1 of 1111. Why it is assigned to no group. What is different from the rails assigned to SoC domain. I cannot find any difference from the SoC rails.

Regards,

Oguri

Hi Oguri-san,

the GPIO11 pin of the TPS65941111 is assigned as a general-purpose output without any readback or other safety mechanism. So the PMICs will not detect an error on GPIO11. However, in the total PDN, GPIO11 is used as EN_3V3IO_LDSW signal to enable an external load-switch for the VDD_IO_3V3 rail. This VDD_IO_3V3 rail can be monitored through the FB_B3 pin of the TPS65941111, as explained in the PDN-0C document. Please note that the system SW must configure the BUCK3_VMON and enable it. Here the I2C commands:

Write 0x4C:0x12:0xFD:0x00 // Set BUCK3 to 3.3V

Write 0x4C:0x14:0x73:0x00 // Set BUCK4 to 1.1V

Write 0x4C:0x09:0x07:0xF1 // Set BUCK3 slew rate to 0.31mV/us

Write 0x4C:0x0B:0x07:0xF1 // Set BUCK4 slew rate to 0.31mV/us

Write 0x4C:0x41:0xA0:0x0F // Map BUCK3&4 to SOC rail group

Write 0x4C:0x4A:0x33:0xCC // Mask BUCK3&4 OV/UV

Write 0x4C:0x08:0x10:0xEF // Enable BUCK3 Monitor

Write 0x4C:0x0A:0x10:0xEF // Enable BUCK4 Monitor

Write 0x4C:0x4A:0x00:0xCC // Unmask BUCK3&4OV/UV