LM5114: Output high glitch from gate driver

Hi Tony,

Thanks for reaching out!

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1)  If the P_OUT pin of the driver is going a diode drop (0.3V) above the supplied VDD, there will be conduction through the body-diode of the P-FET.  If the power going through the body diode of the MOSFET output structure of the gate driver is too great, this can cause damage to the device and ruin it.  This can also result in noise from the output being conducted onto the VDD rail of the device; which can move the VDD based input logic thresholds, and can add unwanted noise into the inputs, which can cause false-signals.

2)  It also looks like the large transient could be pushed into the System GND thought the body diode(s) of the output stage of the driver too.

3)  The cause might be hard to pin-point here... It looks likely that the GND of the gate driver is riding on a lot of noise.  This could also be shifting your GND voltage.

4)  For more failure mode testing, measuring the impedance of a fresh device off of the board and then measuring another device off the board that you think is messed up can help guide you to where the damage is.

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My Questions:

a)  What kind of test is this?  Short circuit test?

b)  What external variables are causing this behavior?

c)  Do you have waveforms of VDD during the failure?

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I look forward to hearing back!

Thanks,

Aaron Grgurich

Hi Aaron, 

Thank you so much for your reply. 

First, to answer your questions: 

a)  What kind of test is this?  Short circuit test?

This is a bit of a nonstandard test. We were feeding a short bursts of high duty cycle PWM into the inverter as we found that doing so produced a failure that is very similar to what we experienced before (e.g. several of the paralleled FETs blew up and the local voltage regulator failed short), in order to get information on the failure chain. (For the record, there probably wasn’t such a signal during the original failure.)

b)  What external variables are causing this behavior?

We haven’t established anything to be causative yet, since we have yet to replicate the gate driver glitch outside of the inverter system (as it fails). However, prior to the behavior, the voltage regulator fails and subjects the gate driver to 11V average with ~10us spikes up to about 22V. It seems like the glitches happen when the supply voltage changes over a lower voltages range. The load is one GS66508T per gate driver with 4.7 ohm pull up and pull down resistors. The signal into the gate driver is 100 cycles at 13MHz and 90% duty cycle every 10ms. 

c)  Do you have waveforms of VDD during the failure?

The VDD waveform was captured on a separate scope (in yellow), and I have overlaid the corresponding trace for the first glitch. 

I believe the craziness of VDD has to do with some failure of the input supply (pink trace).

I appreciate you bringing up body diode conduction. Now looking back at the oscillogram, it does seem that the gate is below the driver output after the pulses end. I am not sure if it is biased enough to harm anything per se. If the difference is to be trusted (probably not), there is maybe 100mA or so going out the NMOS diode. 

Do you know what current can be sustained before latch-up is a possibility? 

Interestingly, the gate drivers seem to still appear to work as normal after the failure of the other stuff. We haven’t done any really extensive measurements but the ones we’ve tested don’t draw excessive supply current and do replicate an input signal. 

I will have to think a bit about the possibility of ground bounce which you mentioned. Currently we don’t really have major ground loops that I know of; everything is referenced together at the inverter region. However, within and between the inverters there are potential loops. 

So, for the output behavior that we saw,

Is it possible for the output to get stuck high when VDD drops too far below 4V? Or is it more likely an input signal issue? 

Are there any potential causes for the output high other than a corresponding input signal? I know that that is a possibility but it seems quite extraordinary for the input to reach 3.3V and stay >1.6V while the measured input signal has hardly any indication of being anything other than ~0 (though there is some wobble once the current starts going). 

I hope I was able to make my situation more clear. Let me know if there’s anything else you’d like to know, and thanks again for the help. 

Best regards, 

Tony

Hello Aaron, 

Yes, we are having the voltage regulator/VDD supply fail first, and that subjects the gate drivers and GaN HEMTs to stresses outside their ratings. 

So there is no blame to TI however the LM5114 behaves. We just want to understand what is happening, since it seems like the gate driver is turning on unexpectedly, which is what then killed the HEMTs in our test, and probably in the original failure as well. (Given enough time the overvoltage would have done it, but in this case, the failure is pretty certainly caused by a high output from the gate driver, since a second paralleled inverter, which had the input signal shorted to ground, also experienced the same failure.) 

I don't think the original images were very easy to read, so I labelled the traces here for reference. 

At this point, the HEMT seems to at least still be operational. It is switching, as seen by the drain waveforms, and since we were measuring before and after a single 4.7 ohm gate resistor with the one we were probing, we can get an idea for the gate current, though I think there's some ground shift at the end of the labelled event, which does add uncertainty. 

We have tried driving VDD to voltages similar to what we observed during the failure but didn't see any output glitches. And definitely we will need to change the supply design, however, at this stage we are trying to understand the failure, of which the LM5114's (to us) unexplained behavior was a major part.

So yeah, we're looking for a good explanation for why the output of the LM5114 is going high there. Again, no problem with TI or the LM5114 but since you understand the part better, if it is the gate driver producing the glitch (which the oscillogram seems to indicate), then you'd have a better idea.

Thanks, 

Tony

Hello Tony,

Aaron is out of the office at the moment, but should respond to your recent post within the next day.

Regards,

Sorry for the delay.

We have done a few more tests on the gate drivers. It seems like there is an output pulse correlated with a rising supply voltage at around 3.8V (maybe related to the UVLO threshold?) which appears on the gate drivers that were involved in the failure, but not the ones which were “unstressed.” There also appears to be a “healing” effect as the problem, from the outside, gradually reduced as the test was repeated.

Last Friday we talked about this issue with our partner, Lam Research, who suggested that we try to get in contact with the designer(s) of the LM5114. If that is possible, please let me know.

Best thanks,
Tony

Hello Tony,

Aaron is out of the office at the moment, but should respond to your recent post within the next day.

Regards,

Hi Alexander, 

Thanks for the suggestion. 

The slew rate in our current test is not terribly high, maybe 0.2V/us. Additionally, we haven't been able to produce these glitches, even with higher VDD slew rates, on gate drivers that weren't stressed by the failure. It very much seems like a case of subtle damage, though the mechanism and characteristics are still unclear.

I will try the test you mentioned as it will be useful to know how sensitive the LM5114 is to VDD slew rate before they are damaged, since we use it a lot in our designs. 

Regards, 

Tony

Hi Tony,

Understood and thanks for the slew rate information.

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Since the device is being subjected to voltages beyond what the datasheet says is acceptable, there is likely damage.  This damage may be subtle as you said, and allows the device to still work, but with potential minor quirks as we are experiencing here.

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Sounds good, hopefully the tests provide some clarity here.  I think before investigating the gate driver, the power rail should be fixed first.

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Thanks!

Aaron Grgurich