LM5176: Asking for the LM5176 design suggestion

SHH

Mastermind 32256 points

Part Number: LM5176

Hi Sir,

My customer would like design LM5176

Would you please review the high low side Vds waveform to see any short through risk?

Thanks for help!

CH1: high side Vgs

CH2: Vin

Ch4: low side Vgs

Here is the waveform and MOS spec

BR,

SHH

over 3 years ago

0 Youhao Xi over 3 years ago

TI__Guru* 78510 points

Hi SHH,

If the waveforms are real, you may have a shoot-through event during LDRV turn on. The waveforms also clearly show about 35ns dead time by the LM51765, but the circuit may induce some gate ringing due to parasitic inductance on the PCB. This leads to the math trace jumping up mostly exceeding the high side FET's gate threshold voltage.

However, I am afraid the waveforms may be affected by probing and not realistic. In you current picture, I am afraid you just got Vg but not Vgs for the low side FET. Note that there is sense resistor at the source of the low side FET, and you need to exclude its effects.

Please retest the by twisting C1 and C3 probe's ground leads together, and also use two other probes to test the low side Gate and Source by twisting the two ground leads and do a math as you do for the high side FET Vgs.

Thanks,

Youhao Xi, Applications Engineering

0 SHH over 3 years ago in reply to Youhao Xi

TI__Mastermind 32256 points

Hi Youhao,

thanks for feedback.

Would you please review the following waveform and provide your comment?

i=imax

in case image compressed on E2E, upload the original image again here.

6131.Waveform.zip

BR,

SHH

0 Youhao Xi over 3 years ago in reply to SHH

TI__Guru* 78510 points

Hi SHH,

What is VPR6? Is R6 the current sense resistor?

Anyway, the last two waveforms are very good. The first two waveforms shows an induced high side voltage (HVgs) after the low side FET is turning on. You can also see the ringing on the low side Vgs. Since the induced LVgs is approaching 2V, it may be a potential risk of shoot-through. You may consider to insert a small gate resistor (suggesting not >5 Ohm) and see if the induced HVgs can be reduced.

Thanks,

Youhao

0 SHH over 3 years ago in reply to Youhao Xi

TI__Mastermind 32256 points

Hi Youhao,

I will check with customer.

There are two questions.

1. is that normal there is an inrush current during power up?

2. In IC voltage stress test experiment, there are some fail in SW, HDRV, LDRV, BOOT,

BOOT with respect to SW & BIAS, Is there any more detail PIN MAX &MIN voltage test SPEC than 7.1 absolute max rating?

BR,

SHH

0 Youhao Xi over 3 years ago in reply to SHH

TI__Guru* 78510 points

Hi SHH,

It not a surprise that there may be inrush current during startup to charge up the output capacitor bank. Are the green trace the signal or different signals in the two scope pictures?

Regarding the rating, the EC table that you referred to lists the abs max voltage ratings of each pin reference to another pin as indicated, and the ratings are guaranteed.

Could you share your schematic for an review?

Thanks,

Youhao

0 SHH over 3 years ago in reply to Youhao Xi

TI__Mastermind 32256 points

Hi Youhao,

please refer to the scheamtic and files here.

cusotmer measure current on the inductor PL1 (15uH).

https://txn.box.com/s/l8o9fo7sjlohhovjxgf8fxwhlk706jq5

here are the stress failed items, would you please review and provide your comment? thanks for help!

BR,

SHH

0 Youhao Xi over 3 years ago in reply to SHH

TI__Guru* 78510 points

Hi SHH,

The files are protected by password. Could you email me the password?

Thanks,

Youhao

0 SHH over 3 years ago in reply to Youhao Xi

TI__Mastermind 32256 points

Hi Youhao,

LM5176 operate at higher Vin and Vout in customer's application.

all the pin's min voltage are -0.3V.

Is there any transienet min value as SW1 and SW2 pins?

or for the fail items, is there any way to tune to fit the spec? Thanks for help!

BR,

SHH

0 Youhao Xi over 3 years ago in reply to SHH

TI__Guru* 78510 points

Hi SHH,

We only specify, and characterize, the SW pins with transient rating. Other pins usually do not see a negative pulse in normal use, and we do not have data to share about the transient min rating for other pins.

I will take a review of the files tomorrow.

Thanks

Youhao

+1 Youhao Xi over 3 years ago in reply to Youhao Xi

TI__Guru* 78510 points

Hi SHH,

I reviewed the password protected files. There are many items show failing but some cannot be explained. For instance, how could you get PGOOD = 8.72V while the VCC is 7.636V max? PGOOD is an open drain pin pulled by VCC via 100k resistor according to the schematic. It seems to be an test method issue.

Regarding the inrush, was the test done with repetitive input power applications? I am afraid the recycling may be too fast to allow the SS capacitor (100n) to fully discharge before the next power up. Could you check this with the customer?

The drivers are obviously damaged. I cannot see much clue from the schematic. This may be related to layout issue, because improper layout may lead to excessive SW negative pulse and hence overcharge the boot capacitor, or ringing across the boot capacitor due to resonance of the PCB stray inductances and the boot capacitor.

I suggest the customer to take a look of the following series of blogs discussing the layout optimization for the 4-sw buck-boost circuit.

https://e2e.ti.com/blogs_/b/powerhouse/posts/four-switch-buck-boost-layout-tip-no-1-identifying-the-critical-parts-for-layout

https://e2e.ti.com/blogs_/b/powerhouse/posts/four-switch-buck-boost-layout-tip-no-2-optimizing-hot-loops-in-the-power-stage

https://e2e.ti.com/blogs_/b/powerhouse/posts/four-switch-buck-boost-layout-tip-no-3-separating-differential-sense-lines-from-power-planes

https://e2e.ti.com/blogs_/b/powerhouse/posts/four-switch-buck-boost-layout-tip-no-4-routing-gate-drive-and-return-paths

Thanks,

Youhao

+1 Stefan Schauer over 3 years ago in reply to Youhao Xi

TI__Guru 58851 points

Hi SHH,

I have not seen an update for the last 27 days, so I assume the questions are answered.
I close this thread now. If there is still something open reply and the thread will get open again.
If you have any other question or of the thread gets locked, please open a new one.

Clicking the Resolved Button also helps us to maintain this forum.

Best regards,

Stefan

0 SHH over 3 years ago in reply to Stefan Schauer

TI__Mastermind 32256 points

Hi Stefan,

customer measure the SW2 waveform.

Should customer set scope at 1G or 20MHz resolution? the transient is very different.

please refer to waveform and setup here. customer used the shortest ground length.

1G setting

20M Setting

envoriment setup

BR,

SHH

+1 Youhao Xi over 3 years ago in reply to SHH

TI__Guru* 78510 points

Hi SHH,

Happy New Year! Sorry for the delay due to holidays. The spec refers to the SW pin wrt the PGND pin. From the picture, the probe ground lead is not at the PGND pin, and it also forms an antenna with the green wire. Suggest to solder the black wire at the PGND pin, and twist the black and green wires to minimize the false measurement by the probe. I would use 1G bandwidth first to see whether the spec is meet: -5V for 20ns. You use a smaller time scale to see more details of the SW negative pulse.

Thanks,

Youhao

+1 SHH over 3 years ago in reply to Youhao Xi

TI__Mastermind 32256 points

Hi Youhao,

I will loop you in customer mail due to some of the confidential information. thanks for help!

BR,

SHH

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LM5176: Asking for the LM5176 design suggestion