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UCC28950: shortcircuit in Q1 and Q3 of reference design

Eze Bayer
Prodigy 150 points
Part Number: UCC28950

Hello, I am working on a design similar to the reference one, but with 24V 25A output.

I had Vbias ON in the control circuit and looking on an oscilloscope at the rectangular signals from the FET gates. After that, when I connected the 400 VDC input to the power circuit, the circuit lines and FETs (Q2 and Q3) blew up.

Do you know why this can happen?

Before the explosion, I tried a larger R value on the gate control primary (R33 and R34) with a lower control current. In this test I got a 24V 300mA output, but the H-bridge control FETs got really hot and I quickly shut down. I understand that the current and voltage control gate was not sufficient to drive the FETs. Finally I put 3ohm into R33 and R34 as the original circuit when it blew up.

Thanks

Ezequiel

  • 0
    TI__Guru* 85616 points

    Hello,

    If you are using the cycle by cycle peak current limit correctly it should have prevented the FETs from being damaged.  FETs are generally damaged due to over current and/or over voltage.  I would start by double checking the FET current and voltage ratings; as well as, the current limit ratings.

    What reference design are you referring too?

    Do you have a complete schematic that you can share?

    Regards,

  • 0 in reply to Mike O'
    Prodigy 150 points

    Hello Mike, I attach the schematic, I used as reference the design from datasheet, but changing some components for 24V. I used too the tina simulator and function well.

    Could you review my design?

    Thanks

     POWER_24V25A.pdf

  • 0 in reply to Eze Bayer
    Prodigy 150 points

    as additional data, I don't know if it is okay to turn on the control circuit (12V Vbias) before turn on the power circuit

  • 0 in reply to Eze Bayer
    TI__Guru* 85616 points

    Hello,

    I will review this on Monday and give you some feedback.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 150 points

    Thank you very much for your reply! I will wait for your feedback.

  • 0 in reply to Eze Bayer
    TI__Guru* 85616 points

    Hello,

    I reviewed the schematic and it looks O.K.  It is identical to the 600 W EVM and data sheet.  The power level is the same so that you be O.K.  You should have changed the output capacitors, turns ratio of the transformer and SR FETs for the higher output voltage.  I believe you need to change D8 and D9 for higher output rated voltages as well.

    I would double check your layout to make sure it matches.  You might want to double R26 and R27 due to the higher voltage.

    After you double check your layout and if that is O.K. You had mentioned that you ran a tina model and it worked O.K. 

    So you have a reference point for waveforms.  I would suggest loading with 10% resistive load and study the CS signal, the voltage amplifier output, the voltage across the input of the transformer and the SR voltages drain to source.  Just to make sure they match your model.  This will help you identify what the issue as well.  Remember the FETs are most likely getting damaged due to an over voltage/and or over current.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 150 points

    Hello Mike, thanks for your answer, effectively I changed turns ratio of the transformer, output FETs and capacitors. D8 and D9 were selected with 100V 3A rating, it is not enough? I will double R26 and R27 and I will trie again. I can not test CS pin with the circuit withoyt changes because I can not to turn on the circuit.

    I will trie to review a little more and I will tell you news.

    Thanks

    Ezequiel

  • 0 in reply to Eze Bayer
    TI__Guru* 85616 points

    Hello,

    Thanks for letting me know.  Keep in touch.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 150 points

    Hello Mike, I didn't find information about the selection of the value of R26 and R27. Could you give me information about these values?

    Thanks

  • 0 in reply to Eze Bayer
    TI__Guru* 85616 points

    Hello,

    That is to discharge the RCD clamp every switching cycle.  The power rating is ((Vout*2-Vout)^2)/R for these resistors.

    You can select the R based on switching frequency  and 1 to 2% discharge of C10.  You should be able to use the below equation to size R26 and R27 with a little algebraic manipulation.

    (1/fsw)*0.01 = 5*(R26*R27/(R26+R27))*C10

    Regards,

  • 0 in reply to Mike O'
    Prodigy 150 points

    Hello Mike, I'm sorry but I don't understand,  this equation do not match with R and C from evaluation board from datasheet (1Kohm - 1Kohm - 220nF).

    Regards

  • 0 in reply to Eze Bayer
    TI__Guru* 85616 points

    Hello,

    The data sheet and application note did not discuss how to setup an RCD clamp.  However you set up and RCD clamp based on 5 RC time constants.

    fsw = switching frequency and 0.01 is 1%.

    The Resistance for R26 and R27 is too low for your design and I don't believe that it was setup correctly.  With the equation I gave you should be able to select the resistance for R26 and R27.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 150 points

    but for fsw=100KHz and C=220nF -> Rtotal=0.09, what it means?

  • 0 in reply to Eze Bayer
    TI__Guru* 85616 points

    Hello,

    I actually get 9.   This means the 220 nf is quite large for an RCD clamp.  It is only supposed to suppress the leakage energy of the transformer.

    I am looking at this again and I am wondering if C10 is too large for the design.  Sometimes designers just throw down snubber circuits without any thought behind it.  This may be the case.

    C10 the 220 nF capacitor is just supposed to suppress the energy stored in the leakage spike.  Do you know what the secondary side leakage inductance (Lks) is? 

    Once you have Lks you can can can calculate the leakage energy based on the peak secondary winding.

    Ipeak_secondary^2*Llks/2 = Leakage_Energy  

    Once you have that you size C10 to store 10 times the energy.

    10*Leakage_Energy = C10*((2*Vout)^2)/2

    C10 = 10*Leakage_Energy/((((2*Vout)^2)/2)

    Once you have C10 set R6 = (0.01/fsw)/(5*C10)

    R26 and R27 look like they are actually a snubbing network for the ringing.  They were probably made so small because C10 and R6 were not sized correctly.

    Once you resize R26 and R27 you may be able to get away larger resistors to snub the ringing through those resistors.  You are trying to set the snubbing resistor R26 and R27 so the Q of the circuit is 1.  Csw is the secondary switch node capacitance.

    R = 1/Q*(Lslk/Csw)^2

    Regards,