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TLV1117: Schematic review

Kygo Cheng
Expert 6830 points
Part Number: TLV1117

Hi Team,

There is a good new that we  DIN TLV1117DCY!

And there have one thing need your support,

Please help check this SCH, THX

UP1K22R REV H_TLV1117.pdf

  • 0
    TI__Mastermind 46495 points

    Hi Kygo-san,

    I've reviewed the schematics and layout and I have a couple questions.

    1. What is the expected load current for both devices? 12V - 3.3V has the potential for a lot of power dissipation.
    2. Are the output caps ceramic? TLV1117 is a pretty old part and was designed before ceramic caps were popular, and it needs at least 0.2ohm ESR for stability.

    Regards,

    Nick

  • 0 in reply to Nick Butts
    TI__Expert 6830 points

    Hi Nick

    Thank you for your help!

    And I will check with RD!

  • 0 in reply to Kygo Cheng
    TI__Expert 6830 points

    Hi Nick

    After discuss with customer,

    1.The out put current is 0.5A!

    2.May I know the layout is OK? Does customer need to relayout ? THX

  • 0 in reply to Kygo Cheng
    TI__Mastermind 46495 points

    Hi Kygo-san,

    12V - 3.3V @ 500mA is 4.35W dissipated in the LDO. This would correspond to a junction temperature rise of over 400C in the DCY package. This is obviously too much power being dissipated. The options they have are to use additional LDOs in parallel to help spread the power dissipation, or to use a DC/DC to get the voltage down before going into the LDO. 

    To answer your second question, the layout looks fine if there was not so much power being dissipated in the LDOs, but will likely need a relayout because of the issue I mentioned above.

    Regards,

    Nick

  • 0 in reply to Nick Butts
    TI__Expert 6830 points

    Hi Nick

    1. So I need to check below  Red frame Junction-to-ambient thermal ? THX

    2. And could you suggest a solution for this case ?

    And it could meet 12V - 3.3V @ 500mA ,THX

  • 0 in reply to Kygo Cheng
    TI__Mastermind 46495 points

    Hi Kygo-san,

    1. Yes, because they are using the DCY package
    2. The only option they have to use a single TLV1117 for this is if they use a different package. For example, the DRJ package has much better thermal performance (R_θJA = 38.3C/W), and furthermore the R_θJA can be improved upon relative to the datasheet specifications by using a more thermally optimized board layout than the JEDEC board that is used to simulate these thermal metrics. See this app note for more information on this:
      An empirical analysis of the impact of board layout on LDO thermal performance
      The other option is to use a buck regulator to get some of the voltage down before going into the LDO. Of course that requires a lot of extra board space to do so. 

    Regards,

    Nick